Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.     

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects

The influence of via density and passivation thickness on the mechanical integrity of Back-End-Of-Line (BEOL) interconnects under Chip Package Interaction (CPI) loading is evaluated using a dedicated package test chip with 4 metal layers, and advanced copper/low-k processing. The reliability assessment is done using thermal cycling reliability tests, where two dedicated resistance based CPI test structures are analyzed. The data show a correlation between via density and reliability for both passivation modules, where a higher via density reduces the number of failures. In addition, the influence of passivation thickness was determined, where a thinner passivation results in a reduced number of failures. In order to visualize the failures, the interconnect stack was exposed after mechanical removal of the package overmold and Si etching. Cracks were present at the corner of the test chip.     

Modular, device-scale, direct-chip-attach packaging formicrosystems

A pressing challenge to the commercial implementation of prototype microsystems is the reduction of package size and cost. To decrease package size, a process was developed for the fabrication of high-aspect-ratio, through-wafer interconnect structures. These interconnects permit device-scale packaging of microsystems and are compatible with modern surface mount technology such as flip chip assembly. To minimize package cost, a modular wafer-level silicon packaging architecture was devised. Low temperature bonding methods were used to join package components, permitting integration of driving circuitry on the microsystem die. The reconfigurable architecture allows standard package components to serve a wide variety of applications     

超高速光互连系统级封装技术前沿研究

光互连系统级封装技术是用光互连在封装尺度上代替铜互连,以突破目前芯片间通信低速度瓶颈。超高速光互连系统级封装的目标是开发出可集成光子收发器,并嵌入到现代尖端的系统级封装中(SiP)中,以提高并行计算系统的数据传输效率或速度。文章介绍了超高速光互连系统级封装关键技术及前沿研究情况,通过分析IMEC、Intel、BAE系统公司等研究机构的开发现状和技术发展路线,论述了光互连SiP关键技术的发展趋势。     

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm $times$ 6.5 mm with 48 spring contacts on a 0.8 mm $times$ 0.65 mm grid array, each spring measuring 400 $, mu$m $times$ 100 $mu$m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone ${>}20thinspace 000$ hot plate thermal cycles and ${>}1000$ oven thermal cycles without failure.      

Design and Fabrication of FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such “compliant interconnects” are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. This paper presents two concepts to address this. First, an innovative, cost-effective fabrication process to realize compliant interconnects is proposed. Sequential lithography and electroplating processes with up to two masking steps are utilized. Such an approach potentially reduces the cost of fabricating compliant interconnects. Second, an innovative approach to designing compliant interconnects is proposed to improve electrical performance without compromising on mechanical reliability. The new approach uses parallel/multiple electrical paths as part of the compliant interconnect design. These concepts are integrated to realize a new compliant interconnect technology called FlexConnects. Utilizing the proposed fabrication process parallel-path FlexConnects are realized at a 100- $mu{hbox {m}}$ pitch. Numerical simulations are used to demonstrate that the electrical performance of parallel-path FlexConnects (self inductance of $sim$ 37 pH) is enhanced without compromising on mechanical performance, validating the use of parallel/multiple electrical paths in the interconnect design.      

Bed of Nails—100- $mu$m-Pitch Wafer-Level Interconnections Process

The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-mum pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 mum and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10times10mm²size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40degC to 125degC show promising results.     

Wafer-level package interconnect options

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution.     

Chip-to-Board Micromachining for Interconnect Layer Passive Components

Integrated inductors are typically formed either on a chip or embedded in a package or board. In this work, we explore the possibility of forming inductors in the chip-to-board interconnect layer. The solderless technique of copper (Cu) electroplating bonding is used to simultaneously form inductor structures as well as chip-to-board interconnect. The use of the gap between the chip and substrate for inductors not only increases integration density, but also allows large magnetic cross-sectional areas to be achieved. To demonstrate the technology, a plating-through-mold method has been used in the establishment of tall interconnect or solenoid inductors. For demonstration of the electroplating bonded micro solenoid structures, three- and seven-turn (500mum in height) inductors have been realized with measured inductances of 3.6 and 10.4nH, and Q-factors of 71 and 55, respectively. As an alternative approach, a polymer-core-conductor method in which polymer posts coated with metal are electroplating bonded, has been developed. This approach reduces processing time in the fabrication of the tall metal structures. For the polymer core RF structures, three-, five-, seven-, and 10-turn inductors have been fabricated. These inductors have inductances of 4.2, 7.0, 9.6, and 13.6nH, and Q-factors of 72, 64, 56, and 61, respectively     

集成电路芯片上光互连研究的新进展

讨论了集成电路向高集成度、高工作频率和高传输速率继续发展时 ,常规金属互连出现的困难以及集成电路芯片上光互连具有的潜在优势 .介绍了组成芯片上光互连的光发射器件、光接收器件和光传输器件等三种基本器件及其与硅集成电路集成的研究新进展 .最后展望了集成电路芯片上光互连的应用前景 .     

Wireless communication in a flip-chip package using integrated antennas on silicon substrates

An intrachip wireless interconnect using integrated antennas is demonstrated in a flip-chip ball grid array package. The wireless interconnect consists of a transmitter-receiver pair, which is fabricated in a 0.18-/spl mu/m CMOS process. A 15-GHz signal is generated and broadcasted across the integrated circuit. The signal is picked up by a receiver 4 mm away on the same integrated circuit and frequency divided by eight to produce a 1.875-GHz local clock signal. The interconnection is also demonstrated between a transmitting antenna and a packaged receiver 40 cm away from the transmitting antenna. Demonstration of intrachip wireless interconnects in a package has been considered the ultimate test for this technology.     

Highly Conductive,Flexible, Polyurethane‐Based Adhesives for Flexible and Printed Electronics

Flexible interconnects are one of the key elements in realizing next‐generation flexible electronics. While wire bonding interconnection materials are being deployed and discussed widely, adhesives to support flip‐chip and surface‐mount interconnections are less commonly used and reported. A polyurethane (PU)‐based electrically conductive adhesive (ECA) is developed to meet all the requirements of flexible interconnects, including an ultralow bulk resistivity of ≈1.0 × 10^?5 Ω cm that is maintained during bending, rolling, and compressing, good adhesion to various flexible substrates, and facile processing. The PU‐ECA enables various interconnection techniques in flexible and printed electronics: it can serve as a die‐attach material for flip‐chip, as vertical interconnect access (VIA)‐filling and polymer bump materials for 3D integration, and as a conductive paste for wearable radio‐frequency devices.     

Substrate interconnect technologies for 3-D MEMS packaging

We report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at different elevations on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 μm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.     

Thermal-Mechanical Process Simulation of an Advanced NCF Technology

The paper introduces an advanced nonconductive film (NCF) typed FC technology employing a novel compliant composite interconnect structure. The interconnect reliability and bondability of the technology are demonstrated through experimental thermal humidity (TH) test in conjunction with a two-point daisy chain resistance measurement. The alternative goal of the study aims to look into the insight of the thermal-mechanical behaviors of the novel packaging technology during NCF bonding process and thermal testing through numerical modeling and experimental validation. For effectively simulating the bonding process, a process-dependent finite-element (FE) simulation methodology is performed. The validity of the proposed methodology is verified through several experimental methods, including a Twyman-Green (T/G) interferometry technique for warpage measurement, and a four-point probe method for contact resistance measurement. At last, a design guideline for improved process-induced thermal-mechanical behaviors is presented through parametric FE analysis. Both numerical and experimental results demonstrate the feasibility in applying the novel compliant interconnects to achieve a proper contact stress at various temperature environments so as to hold a low and stable connection resistance at elevated temperature. Most importantly, the novel interconnects survive the 85degC/85%RH TH test for 500 hours.     

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the state of the art of their interconnect-related fabrication and modeling efforts is reviewed. Both electrical and thermal modeling and performance analysis for various CNT- and GNR-based interconnects are presented and compared with conventional interconnect materials to provide guidelines for their prospective applications. It is shown that single-walled, double-walled, and multiwalled CNTs can provide better performance than that of Cu. However, in order to make GNR interconnects comparable with Cu or CNT interconnects, both intercalation doping and high edge-specularity must be achieved. Thermal analysis of CNTs shows significant advantages in tall vias, indicating their promising application as through-silicon vias in 3-D ICs. In addition to on-chip interconnects, various applications exploiting the low-dimensional properties of these nanomaterials are discussed. These include chip-to-packaging interconnects as well as passive devices for future generations of IC technology. Specifically, the small form factor of CNTs and reduced skin effect in CNT interconnects have significant implications for the design of on-chip capacitors and inductors, respectively.      

Materials characterization of the effect of mechanical bending on area array package interconnects

The mechanical integrity of solder joint interconnects in PWB assemblies with micro-BGA, chip scale, and land grid array packages is being questioned as the size and pitch decrease. Some consumer products manufacturers have mechanically reinforced fine pitch package interconnects with an adhesive underfill, and others are evaluating the need for underfill on a case-by-case basis. Three-point cyclic bend testing provides a useful tool for characterizing the expected mechanical cycling fatigue reliability of PWB assemblies. Cyclic bend testing is useful for characterizing bending issues in electronic assemblies such as repetitive keypad actuation in cell phone products. This paper presents the results of three-point bend testing of PWB assemblies with fine pitch packages. The solder joints on ceramic components performed better than a laminate interposer component in bend testing, because of the stiffening effect of the ceramic packaging materials. The methodology of materials analyses of the metallurgy of solder interconnects following mechanical bending and thermal cycle testing is described. The microstructure and fracture surfaces of solder joint failures in bend test samples differed significantly from thermal cycle test samples.     

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to that used for stencil printing. Greater versatility of solder materials can be obtained through solder paste than the electroplating. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118 ± 3.5 μm, and a maximum-to-minimum bump height range of 17 μm over a 150 mm-diameter wafer and have been produced repeatedly on test wafers with 210 μm peripheral pitch. A 109.6 ± 1.3 μm bump height on orthogonal array with 250 μm pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10 × reflows and 1008 h of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55°C to +125°C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 h of autoclave stress at 121°C, 100% RH, 15 psig test condition     

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

Void control during plating process and thermal annealing of through-mask electroplated copper interconnects

The quality of the sputtered copper film, which serves as the seed layer for sequent electroplating, becomes critical when the size of crack on the surface of the sputtered film is close to the feature size of the electroplated copper interconnect. The crack results in void formation in electroplated copper before thermal annealing and this phenomenon limits attainable highest anneal temperature. To solve this problem, the sputtered seed layer was slightly etched before electroplating process and a TaN passivation layer was deposited on the electroplated Cu interconnect before thermal annealing. Those processes not only suppressed void formation during the electroplating and annealing process at 300 °C, but also resulted in lower electrical resistance in the copper interconnects.