A novel wideband low phase noise 2:1 frequency divider

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider.Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques,the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm2 of the core die area.     

A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS

A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF). An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-μm technology occupies 0.09 mm²; it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V. Operation of 5.5 GHz with 300-mV_pk single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5 GHz input     

18 GHz low-power CMOS static frequency divider

A pseudo-differential latch circuit is investigated. By removing the current source from the conventional source-coupled field-effect-transistor logic (SCFL) structure, the speed of the circuit can be improved. The pseudo-differential D-type flip-flop-based 2:1 static frequency divider, which can operate up to 18 GHz and consumes less than 4 mA from a 1.8 V supply, has been realised in 0.18 /spl mu/m standard digital CMOS technology.     

A 15-GHz broad-band /spl divide/2 frequency divider in 0.13-/spl mu/m CMOS for quadrature generation

This letter presents a 0.13-/spl mu/m CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of the loop gain phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15GHz, featuring a 31% locking range. The divider dissipates 3mA from a 1.2-V power supply.     

基于0.13 μm CMOS工艺的低电压高速1:2分频器设计

在光纤传输系统中,分频器是工作在最高频率的电路之一,起着至关重要的作用,本文就采用了由锁存器构成的数字1:2分频器.采用UMC 0.13μm CMOS工艺,设计了电源电压为1V,工作频率范围为5～20GHz的1:2分频器电路.该电路由基本分频器单元以及输入输出缓冲组成.基本分频器单元采用单端动态负载锁存器.整体电路功耗...     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

一种射频可编程N分频器的设计

提出了用射频CML技术设计的2/3分频单元.基于2/3分频单元,使用0.35 μm SiGeBiCMOS工艺,实现了射频可编程N分频器.验证结果表明,电路可在GHz频率下正常工作,具有相噪低、功耗小等特点.在3 GHz射频输入信号频率下,频偏100 kHz的输出相位噪声为-143dBc/Hz.电路消耗的总电流仅为4 mA(3 V单电源电压),功耗仅为12 mW.     

A 40-GHz Flip-Flop-Based Frequency Divider

This brief presents the design and implementation of a 40-GHz flip-flop-based frequency divider which incorporates a novel latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode. The proposed topology will speed up the latch operation and increase the driving capability. It is capable of performing frequency division at 40 GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18-mum SiGe BiCMOS process, where only CMOS transistors were used. It draws an average current of 5 mA from a 1.8-V supply voltage     

Harmonic-suppressed quadrature-input frequency divider for OFDM systems

A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed.The frequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals.Compared with conventional dividers,the circuit achieves an output I/Q phase sequence that is independent of the input I/Q phase sequence.Moreover,the third harmonic is effectively suppressed by employing a double degeneration technique. The desig n is fabricated in TSMC 0.13-μm CMOS and operated at 1.2 V.While locked at 8.5 GHz,the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset.The circuit achieves a locking range of 15%while consuming a total current of 4.5 mA.     

A 5-GHz programmable frequency divider in 0.18-μM CMOS technology

A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler (DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm; the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

A CMOS Multi-Phase Injection-Locked Frequency Divider for V-Band Operation

An inductor-less injection-locked frequency divider for high-speed frequency synthesis at V-band is presented. It achieves division by six and operates up to 65 GHz. In addition, it can achieve division ratios of four and two when 44 GHz or 22 GHz input signals are applied, respectively. Implemented in a 0.13 mum digital CMOS technology, the divider draws an average current of 18 mA, and the core area is 0.026 mm² .     

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP₃) is -3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.     

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process

With the rapid evolution of wireless communication technology,integrating various communication modes in a mobile terminal has become the popular trend.Because of this,multi-standard wireless technology is one of the hot spots in current research.This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications.High-speed divider-by-2 with traditional sourcecoupled-logic is designed for very wide band usage.Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step.The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider.△-Σ modulator is achieved by an improved MASH 1-1-1 structure.This structure has excellent performance in many ways,such as noise,spur and input dynamic range.Fabricated in TSMC 0.18 μm CMOS process,the fractional-N frequency divider occupies a chip area of 1130 × 510μm2 and it can correctly divide within the frequency range of 0.8-9 GHz.With 1.8 V supply voltage,its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.     

Current Reusing VCO and Divide-by-Two Frequency Divider for Quadrature LO Generation

For low-power and accurate quadrature local oscillator (LO) signal generation, an LC-tank voltage controlled oscillator (VCO) operating at double the required LO-frequency reuses the bias current of divide-by-two frequency divider. The current reusing VCO and divide-by-two frequency divider are targeted to generate the LO signals for a 1.57 GHz global positioning system receiver. Implemented in a 0.18 mum CMOS technology, the current reusing VCO and divide-by-two frequency divider consumes 1.7mA from a 1.8 V supply. The measured phase noise is -120dBc/Hz at 1 MHz offset when the carrier frequency is 1.57GHz.     

An improved current mode logic latch for high‐speed applications

In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.     

A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBTtechnology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology     

应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

Ultra-Low-Voltage 20-GHz Frequency Dividers Using Transformer Feedback in 0.18-$mu$ m CMOS Process

This paper presents the design and analysis of ultra- low-voltage (ULV) high-frequency dividers using transformer feedback. Specifically, a differential-input differential-output injection-locked (IL) divider topology with transformer feedback and a wideband transformer-coupled (TC) divider with quadrature outputs are demonstrated, both of which can operate well at supply voltages as low as the device's threshold voltages. Fabricated in a standard 0.18-mum CMOS process, the ULV-IL divider measures an input frequency range from 16.1 GHz to 20 GHz while consuming a total power from 2.75 mW to 4.35 mW at 0.5 V supply, and the TC-divider measures an input frequency range of 27.8% from 15.1 GHz to 20 GHz with IQ sideband rejection of - 31 dBc while consuming power from 11.4 mW to 13.6 mW at 0.6 V supply.     

39.5-GHz static frequency divider implemented in AlInAs/GaInAs HBTtechnology

A static divide-by-4 frequency divider operating at 39.5 GHz with a corresponding gate delay of 12.6 ps was implemented using InP-based HBT technology. The AlInAs/GaInAs HBT devices utilized in the divider incorporated a graded emitter-base (E-B) junction and had a unity gain cutoff frequency, maximum frequency of oscillation, and current gain β of 130 GHz, 91 GHz, and 39, respectively. The divider was operated with a 3-V power supply and consumed a total power of 425 mW (77 mW per flip-flop). The divider functional yield was over 90%. The operating frequency of this circuit is the highest ever reported for a static divider     

A Frequency Divider Implemented With a Subharmonic Mixer and a Divide-by-Two Divider

This letter proposes a divide-by-four injection-locked frequency divider (ILFD) with the use of a subharmonic mixer and a divide-by-two frequency divider (D2FD). The D2FD circuit consists of a two-stage differential CMOS ring oscillator with n-MOS switches directly coupled to its differential outputs, the measured phase noise of the D2FD is -97 dBc/Hz at 1-MHz offset from the free running frequency of 1.08GHz. The low-voltage CMOS divide-by-four FD (D4FD) has been implemented with the UMC 0.18-mum 1P6M CMOS technology and the power consumption is 9 mW at the supply voltage of 1.2 V. At the input power of 0 dBm, the D4FD can function properly with about 330-MHz locking range from 4.15 to 4.48GHz