Improving electrical performance of Cu/porous ultra-low k dielectrics single damascene lines

An additional dielectric barrier layer SiCN was deposited on the sidewalls prior to Ta(N) metal barrier deposition. It was found that the leakage decreased with three to four orders of magnitude and breakdown voltage increased 200% compared with that without SiCN layer after burn-in at 200/spl deg/C for 40 h.     

Grain morphology of Cu damascene lines

The evolution of the grain structure through annealing of narrow damascene Cu interconnects is important for any further design of highly integrated circuits. Here we present a comprehensive transmission electron microscopy study of damascene lines between 80 nm and 3000 nm wide. Experimental results clearly indicate that morphology evolutions through annealing are strongly influenced by the line width. If the lines are wider than 250 nm a strong connection between the grain structure within the lines and the overburden copper is present at least after sufficient annealing. Once the lines are as small as 80 nm the grain structure within the lines are only weakly connected to the overburden copper grown above.     

Effect of in-line electron beam treatment on the electrical performance of Cu/organic low-k damascene interconnects

The interface quality and reliability issues have shown significant importance in Cu/organic low-k damascene integration. In this letter, a post-etch in-line electron beam (E-beam) treatment was used to modify the interface properties of sidewall barrier/organic low-k dielectric without impairing either the film properties or the dielectric constant. X-ray photoelectron spectroscopy (XPS) analysis indicated that oxygen content at the low-k surface, which mostly came from oxygen/moisture intake from ambient during process, was eliminated by E-beam exposure and subsequent rapid thermal annealing. As a result, Cu/organic low-k interconnects exhibited a lower line-to-line leakage current and a higher breakdown strength. The interconnect structures, after this in-line E-beam treatment process, also showed a good reliability performance against thermal stress, with good leakage current characteristics after a 500-h burn-in at 200/spl deg/C.     

Diffusion barrier performance of W/Ta-W-N double layers for Cu metallization

In this work, the properties of Cu/W/Ta-W-N/Si film stacks were studied. Adding a thin W layer to a stable Ta-W-N diffusion barrier significantly affected the whole metallization system. The introduction of a thin W interlayer caused a significant change of the system while increasing the stability of the film. The tandem barrier was demonstrated to be stable up to 800 °C by the performed analytical barrier tests.     

Relationship between grain structures and texture of damascene Cu lines

The anisotropic spread of the central peak in a (111) pole figure by x-ray diffraction (XRD) was observed for damascene Cu lines of 0.18–2 μm in width and 0.5 μm in depth. The spread originates from the existence of slightly tilted (111) grains because of inclined sidewalls. The tilted (111) orientation is favorable only for polygranular clusters whose sidewall energies can be minimized simultaneously. Consequently, bamboo grains have an exact 〈111〉 orientation, while the polygranular clusters have a tilted 〈111〉 orientation. Using this concept, the volume fraction of the bamboo grains and polygranular clusters in the damascene Cu lines were quantified using the XRD pole plots.     

Fatigue of damascene copper lines under cyclic electrical loading

Fatigue in damascene copper lines has been investigated by using alternating currents to generate cyclic temperatures and stresses/strains. Interconnects using beyond 65 nm node design rules and materials have been studied. We demonstrate here that cyclic thermal strains lead to Cu or Cu/Co-based cap surface modification and open circuits in Cu lines during the application of an alternating electrical current. We underline that the narrower the copper lines are, the more reliable they are and the major role of the cap layer to improve the Cu lines reliability.     

Single damascene integration of porous Zirkon™ version 1 low-k dielectric films

Zirkon™ LK2000 version 1 dielectric film (Zirkon™ is a trademark of Shipley Company L.L.C), a porous methylsilsesquioxane (MSQ)-based spin-on dielectric with a k value targeted at 2.0, has been integrated in single damascene structures. For patterning, a dual SiC/SiO₂ CVD hard-mask was used. Surface treatments (DUV ozone (DUV-O₃), plasma treatments) were tested to solve the adhesion issues encountered at the CVD hard-mask and the low-k interface. Adhesion is only improved when plasma treatments are used. Analyses (FTIR, TDS, nano-indentation) show that the plasma treatments only modify the low-k surface. For integration, a plasma treatment (He, NH₃, N₂/O₂) prior to deposition of the CVD hard-mask was included. After patterning, copper metallization and CMP of the wafers, electrical evaluation shows that, compared to the reference wafer (no plasma treatment), plasma-treated wafers have a higher yield and a lower sheet resistance. The RC delay is slightly higher for the plasma-treated wafers than for the reference wafer.     

Leakage mechanism in Cu damascene structure with methylsilane-dopedlow-K CVD oxide as intermetal dielectric

This letter investigates the leakage mechanism in the Cu damascene structure with methylsilane-doped low-k CVD organosilicate glass (OSG) as the intermetal dielectric (IMD). The leakage between Cu lines was found to be dominated by the Frenkel-Poole (F-P) emission in OSG for the structure using a 50-nm SiC etching stop layer (ESL). In the structure using a 50-nm SiN ESL, the leakage component through SiN also made a considerable contribution to the total leakage in addition to the bulk leakage from trapped electrons in OSG. An appropriate ESL of sufficient thickness is essential to reduce the leakage for application to a Cu damascene integration scheme     

Effects of material interfaces in Cu/low-/spl kappa/ damascene interconnects on their performance and reliability

The performance and reliability of Cu/Low-/spl kappa/ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-/spl kappa/ damascene interconnect is crucial for the high reliability and performance.     

Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization

Integration of Cu with low k dielectrics provided solution to reduce both resistance-capacitance time delay and parasitic capacitance of BEOL interconnections for 130 nm and beyond technology node. The motivation of this work is to study and improve electrical and reliability performance of two-level Cu/CVD low k SiOCH metallization from the results of diffusion barrier deposition schemes. Barrier deposition schemes are (a) high-density-plasma 250 Å Ta; (b) surface treatment of forming gas followed by high-density-plasma 250 Å Ta and (c) bi-layer of 100 Å Ta(N)/150 Å Ta. In this work, we demonstrated the superior and competency of high-density-plasma Ta deposition for Cu/CVD low k metallization and achieved excellent electrical and reliability results. Wafers fabricated with high-density-plasma Ta barrier scheme resulted in the best electrical yields, >90% for testing vehicles of dense via chains (via size=200 nm) and interspersed comb structures (width/space=200 nm/200 nm). Dielectric breakdown strength of the interspersed comb structures obtained at electric field of 0.3 MV/cm was ∼4 MV/cm.     

Microstructure and electromigration in copper damascene lines

Grain sizes and crystallographic orientations of Cu were analyzed versus linewidth in damascene Cu interconnects. Pure bamboo lines were not obtained because grain size decreased as linewidth was reduced. Comparison of electromigration results, for wide line Chemical vapor deposition-Cu (3 μm) polycrystalline structure, and narrow lines (0.5 μm) quasi-bamboo structure, provided almost the same activation energy E_a0.65 eV, even though the poor (2 0 0) texture has rotated in the film plane for the narrow damascene lines. These results are in agreement with copper diffusion involving surface diffusion. Besides, even with a polycrystalline crystallographic orientation, PVD-Cu samples showed a better activation energy value E_a=1.02 eV.     

Study of Ta-barrier and pore sealing dielectric layer interaction for enhanced barrier performance of Cu/ultralow /spl kappa/(/spl kappa/<2.2) interconnects

For Cu/ultralow /spl kappa/ application, understanding of interfacial interaction between Ta and pore-sealing layer over porous dielectric is very important in order to achieve a good barrier performance. However, characterizing the effect of pore-sealing layer on barrier performance poses a big challenge. Most studies monitored degradation of the electrical performance of the Ta barrier after integration process with little discussions on interfacial interaction. In this letter, the interaction at the interface between Ta and pore-sealing layer deposited over porous SiLK (/spl kappa//spl sim/2.2) film is investigated. The barrier performance is improved significantly by nitrogen incorporation during liner growth. This methodology is very effective for improving metal barrier and pore-sealing performance for Cu/ultralow /spl kappa/ interconnects.     

Textural and microstructural transformation of Cu damascene interconnects after annealing

Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min. The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling (FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits.     

Electromigration failure distributions of dual damascene Cu /low – k interconnects

The reliability of dual damascene Cu/low – k interconnects is limited by electromigration – induced void formation at vias. In this paper we investigate via void morphologies and associated failure distributions at the low percentiles typical of industry reliability requirements. We show that Cu/low – k reliability is fundamentally limited by the formation of slit – voids under vias. Using experimental and simulation approaches we clarify the practical importance of apparent incubation phenomena associated with this failure mode.     

Effects of semiconductor/dielectric interfacial properties on the electrical performance of top-gate organic transistors

We investigated the effects of varying the properties of the interface between a semiconductor P3HT layer and a dielectric Cytop™ layer on the performances of the resulting transistor devices by comparing the mobilities of devices prepared with bottom gate/bottom contact or top gate/bottom contact architectures. The reduced channel roughness that arose from the thermal annealing step dramatically enhanced the field-effect mobility, yielding the highest mobility yet obtained for a top-gate transistor: 0.12 cm²/V s. High-performance OFETs may be fabricated by controlling the channel roughness and the properties of the interface between the semiconductor and the gate dielectric.     

Overview of dual damascene integration schemes in Cu BEOL integration

An overview of different dual damascene approaches is given. Three approaches - trench first, trench first with metal hardmask, and via first - are described in detail. Trench first is the easiest approach but due to its limitation only suitable for wide ground rules with moderate aspect ratios. Via first is capable to run fine pitches and/or higher aspect ratios but has many problems to reach a proper transition between trench and via. With respect to this transition the trench first with metal hardmask concept seems to be advantageous, but it has its own challenges and problems. This article describes our solutions to these problems.     

Evaluation of sheet resistance and electrical linewidth measurementtechniques for copper damascene interconnect

The effects of the barrier layer and dishing in copper interconnects lead to extra difficulties in measuring sheet resistance (R_S) and linewidth when compared with equivalent measurements on nondamascene tracks. This paper examines these issues and presents the results of simulations that quantify the effects of diffusion barrier layers and dishing on the extraction of R_S from cross type test structures and the effect this has on linewidth measurement     

Electromigration of Cu/low dielectric constant interconnects

Electromigration in damascene Cu/low dielectric constant interconnects with overlayers of CoWP, Ta/TaN, SiN_x or SiC_xN_yH_z and Cu(Ti) interconnects capped with SiN_x was studied. The results showed that the migration fast path in the bamboo-like lines primarily occurred at the interface. Cu lines fabricated with various forms of TaN/Ta liner including PVD TaN, ALD TaN, and PVD body centered cubic α- or tetragonal β-Ta liners were also investigated. Both thin surface layers of CoWP or Ta/TaN and the addition of Ti in the Cu lines significantly reduced the Cu/cap interface diffusivity and remarkably improved the electromigration lifetime when compared with Cu lines capped with SiN_x or SiC_xN_yH_z. Activation energies for electromigration were found to be 1.9–2.4 eV, 1.4 eV, 0.85–1.1 eV, and 1.3 eV for the bamboo-like Cu lines capped with CoWP, Ta/TaN, and SiN_x or SiC_xN_yH_z, and Cu(Ti) bamboo lines capped with SiN_x, respectively. The structural phase of the Ta was found to have an insignificant effect on the Cu mass flow rate. A large via size, thicker liner and/or stable connected exposed liner can provide a longer lifetime and tighter lifetime distribution, at the expense of chip density or effective Cu line conductivity.     

Cu互连线显微结构和应力的AFM及SNAM分析

在ULSI中采用Cu互连线代替Al以增加电子器件的传输速度和提高器件的可靠性，Cu的激活能约为1．2eV，而Al的激活能约为0．7eV,Cu互连线寿命约为Al的3－5倍。Cu大马士革互连线的制备工艺为：在硅衬底上热氧化生成的SiO2上开出凹槽，在凹槽中先后沉积阻挡层Ta和晶种层Cu，然后由电镀的Cu层将凹槽填满，最后采用化学机械抛光将凹槽外多余的Cu研磨掉，Cu互连线的尺寸为：200um长，0．5μm厚，宽度分别为0．35，0．5，1至3μm不等，部分样品分别在200℃，300℃和450℃下经过30min退火。利用原子力显微镜（AFM）和扫描近场声学显微镜（SNAM），同时获得形貌像和声像，分别了Cu大马士革凹槽构造引起的机械应力和沉积引起的热应力对Cu互连线显微结构及可靠性的影响，SNAM是在Topometrix公司AFM基础上建造的实验装置，实验采用的机械振动频率在600Hz-100kHz之间。分析测试结果如下：1．AFM和SNAM可以实现对微米和亚微米特征尺寸的Cu互连线的局域应力分布和显微结构的原位分析。2．采用AFM，TEM、XRD观察和测试了Cu互连线的晶体结构，分析了大马士革凹槽工艺 对Cu晶粒尺寸及取向的影响。平坦的沉积态Cu膜的晶粒尺寸约为100nm；而由大马士革工艺制备的凹槽中的Cu互连线的晶粒尺寸约为70－80nm，凹槽结构抑制了晶粒生长，平坦的沉积态Cu膜有较强的（111）织构；而凹槽中的Cu互连线的（111）织构减弱，（200）和其它的晶体取向分量增强。3．SNAM声阻尼信号对材料局域应力的变化敏感，SNAM声图衬底可显示出局域应力的分布，在沉积态的Cu互连线声图中，金属和SiO2介电层的界面处像衬度强，表明该处为应力较高的区域，而在退火后的Cu互连线的声图中，金属和SiO2介电层的界面处像衬度弱，表明退火后该处应力减小，我们对Cu膜进行了宏观应力的测试，退火后应力值从沉积态的661MPa减少至359Mpa，这与SNAM声成像的结果相符合。     

Electrical performance, reliability and microstructure of sub-45 nm copper damascene lines fabricated with TEOS backfill

The fabrication of narrow Cu trenches using a conformal TEOS backfill approach is shown. Cu trenches with widths down to 30-40 nm were achieved. With an adequate Ta-based PVD barrier and Cu seed layer scheme, narrow Cu lines with high yield were obtained. An increase of the electrical resistivity in the narrowest dimensions was observed as a result of the size effect. Electromigration assessment demonstrated that a bilayer TaN/Ta barrier outperforms the monolayer Ta barrier. Electron backscattering diffraction (EBSD) analysis was carried out to determine grain orientation and texture in narrow copper trenches. For the first time, EBSD data reveal that Cu trenches down to 30-40 nm wide have mostly a random texture. The narrower the Cu lines get, the weaker the (1 1 1) texture with both monolayer and bilayer Ta-based barriers.