A 5 Gb/s transceiver in 0.13μm CMOS for PCIE2.0

This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC’s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm~2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.     

CMOS 5 Gb/s串行接收器

设计了一个使用0.13μm CMOS工艺制造的低电压低功耗串行接收器。它的核心电路工作电压为1V,工作频率范围从2.5 GHz到5 GHz。接收器包括两个1:20的解串器、一个输入信号预放大器以及时钟恢复电路。在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度。测试表明,接收器功耗45 mW。接收器输入信号眼图闭合0.5UI,信号差分峰-峰值150 mV条件下误码率小于10~(-12)。接收器还包含了时钟数据恢复电路,其中的相位插值器通过改进编码方式,使得输出信号的幅度能够保持恒定,并且相位具有良好的线性度。     

CMOS2.5 Gb/s时钟恢复电路设计

设计采用0.35μm CMOS工艺来实现一款CMOS2.5 Gb/s时钟恢复电路。由于0.35μm CMOS工艺的限制,采用了预处理电路加锁相环的电路结构。这种电路结构有利于单片集成且工作速度高。预处理器主要有延迟单元、乘法器和窄带滤波电路构成,可以从NRZ数据中得到时钟信号。锁相环采用二阶的模拟锁相环结构,鉴相器采用Gilbert乘法器,环路滤波器采用无源滤波器,VCO采用3级环形振荡器。     

Design and realization of 1.3?Gb/s off-chip transmission circuitry using 0.35?μm CMOS technology

Low-voltage-differential-signaling (LVDS) is one of the very popular technologies which simultaneously addresses low dynamic power consumption and high data rate transmission in modern high speed circuit applications. In this paper, system level integration design approach is applied to design LVDS transmitter featuring high off-chip data rate. Full wave electromagnetic simulation technique was adopted to accurately characterize possible couplings and parasitic effects induced from the off-chip components which then acted as the termination of the output circuitry. Common mode feedback was included to perform fine tuning on the offset leading to much higher overall precision. Meanwhile, generation of the controlled current and voltage across termination was guaranteed through the introduction of a constant transconductance bias network. The design was implemented using TSMC 3.3?V 0.35???m CMOS technology with overall chip size of 0.923?mm². At a DC power consumption level of 29.4?mW, the LVDS transmitter exhibited an off-chip data rate of 1.3?Gb/s validated through measurements.     

2.5Gb/s CMOS光接收机限幅放大器

采用SMIC 0.18μm CMOS工艺设计了光接收机限幅放大器.该放大器采用全差分结构,利用退化电容技术增加高频时放大器的等效跨导,并在Cherry-Hooper结构里引入有源电感反馈代替传统的电阻反馈来扩展带宽.Hspice仿真结果表明限幅放大器具有46dB的中频增益、3.2GHz带宽,当输入电压信号从3.6mVPP到1.7VPP变化时,50Ω负载线上的输出电压限幅在340mVPP,输出眼图稳定清晰.核心电路功耗20.431mW.     

低电压低功耗CMOS 5Gb/s串行收发器

设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12.     

低电压低功耗CMOS 5Gb/s串行收发器

设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12.     

A 10-b 120-MS/s 45?nm CMOS ADC using a re-configurable three-stage switched amplifier

A 10-b 120-MS/s pipeline analog-to-digital converter (ADC) is implemented in a 45?nm CMOS process. Three-stage amplifiers based on reversed nested Miller compensation and Multipath zero cancellation techniques are employed in the input sample-and-hold amplifier (SHA) and two multiplying digital-to-analog converters (MDACs). A single re-configurable three-stage switched amplifier is shared between two adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs. A charge redistributed input sampling network properly handles both single-ended and differential SHA inputs with a swing range of 1.2?Vpp around a 1.6?V common-mode voltage. The prototype ADC with an active die area of 0.58?mm² consumes 61.6?mW at 120?MS/s and 1.1?V. The measured differential and integral nonlinearities are within ±0.44 and ±0.75?LSB, respectively. At a sampling rate of 120?MHz with a 4.2?MHz sinusoidal input, the measured maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range are 55.6 and 70.4?dB, respectively.     

1.25 Gb/s低功耗CMOS光接收机限幅放大器

设计并实现了用于光纤用户网和千兆以太网光接收机的限幅放大器。电路采用有源电感负载来拓展带宽、稳定直流工作点 ,通过直接耦合技术来提高增益、降低功耗。测试结果表明 ,在从 5 m Vp- p到 5 0 0 m Vp- p,即40 d B的输入动态范围内 ,在 5 0 Ω负载上的单端输出电压摆幅稳定在 2 80 m Vp- p。在 5 V电源电压下 ,功耗仅为1 30 m W。电路可稳定工作在 1 5 5 Mb/s、62 2 Mb/s、1 .2 5 Gb/s三个速率上。     

10Gb/s 2.2V输出CMOS激光驱动器

采用逆向递推设计法,利用TSMC0．18μm CMOS工艺,设计实现了适用于超高速光纤通信系统的激光驱动器电路。核心电路为两级直接耦合差分放大器。电路设计中采用电感并联峰化技术拓展带宽和降低功耗。后仿真结果表明,在1．8V电源供电时,工作速率10Gb／s,输入单端峰峰值为400mV的差分信号,在50Ω的负载上可提供2．2V的输出电压。电路功耗185mW。版图面积为0．9mm〉40．95mm。     

5Gb/s 0.25μm CMOS限幅放大器

采用TSMC 0.25μm CMOS技术设计实现了高速低功耗光纤通信用限幅放大器.该放大器采用有源电感负载技术和放大器直接耦合技术以提高增益,拓展带宽,降低功耗并保持了良好的噪声性能.电路采用3.3V单电源供电,电路增益可达50dB,输入动态范围小于5mVpp,最高工作速率可达7Gb/s,均方根抖动小于0.03UI.此外核心电路功耗小于40mW,芯片面积仅为0.70mm×0.70mm.可满足2.5,3.125和5Gb/s三个速率级的光纤通信系统的要求.     

5Gb/s 0.25μm CMOS限幅放大器

给出了一个90 0 MHz CMOS锁相环/频率综合器的设计,设计中采用了电流可变电荷泵及具有初始化电路的环路滤波器.电荷泵电流对温度与电源电压变化的影响不敏感,同时电流的大小可通过外部控制信号进行切换控制而改变.因此,锁相环的特性,诸如环路带宽等,也可通过电流的改变而改变.采用具有初始化电路的环路滤波器可提高锁相环的启动速度.另外采用了多模频率除法器以实现频率合成的功能.该电路采用0 .18μm、1.8V、1P6 M标准数字CMOS工艺实现.     

10Gb/s0.18μm CMOS预处理芯片

介绍采用0.18μm CMOS工艺设计并实现的光纤通信接收机时钟恢复电路预处理器。核心电路采用乘法器加LC选频器的结构。测试结果表明,该电路可工作在10Gb/s 的输入速率上。     

A 12-Channel,30Gb/s,0.18μm CMOS Front-End Amplifier for Parallel Optic-Fiber Receivers

给出了一个采用TSMC 0.18μm CMOS工艺设计并实现的12路30Gb/s并行光接收前端放大器.电路设计采用RGC结构和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题.测试结果表明,在2pF的寄生电容下单信道传输速率达到了2.5Gb/s,在0.8mVpp输入下得到了清晰的眼图.提出了一种同时采用p 保护环(PGR)、n 保护环(NGR)和深n阱(DNW)的并行放大器隔离结构,有效地抑制了并行放大器之间的串扰,减小了放大器之间的衬底耦合噪声.测量结果表明,这种结构与PGR和PGR NGR相比,在1GHz时放大器之间的隔离度分别提高了29.2和8.1dB,在2GHz时放大器之间的隔离度分别提高了8.1和2.5dB.芯片采用1.8V电源供电,单路前端放大器的功耗为85mW,12路总功耗约为1W.     

2.5Gb/s/ch 0.18μm CMOS数据恢复电路

设计了一个应用于SFI-5接口的2.5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0.18μm CMOS工艺制作了一个单通道的2.5Gb/s/ch数据恢复电路,其面积为0.46mm2.输入231-1伪随机序列,恢复出2.5Gb/s数据的均方抖动为3.3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.     

2.5Gb/s/ch 0.18μm CMOS数据恢复电路

设计了一个应用于SFI-5接口的2.5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0.18μm CMOS工艺制作了一个单通道的2.5Gb/s/ch数据恢复电路,其面积为0.46mm^2.输入231-1伪随机序列,恢复出2.5Gb/s数据的均方抖动为3.3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.     

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dBΩ and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10⁻¹² when the input current amplitude (I_in) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10⁻¹² when I_in ≥9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm², respectively.     

10Gb/s 0.18μm CMOS光发射机芯片

介绍了基于0.18μm CMOS工艺设计的10Gb/s光发射机电路,包括复接器和激光驱动器两部分.仿真结果表明,在1.8V电源电压作用下该电路可工作在10Gb/s速率以上,输入四路单端峰峰值为0.2V的信号时,在单端50Ω负载上的复接输出电压摆幅可达到1.4V以上,电路功耗约为230mW.芯片面积为1.77mm×0.94mm.     

A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes

This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer （FFE） and a two-tap half-rate decision feedback equalizer （DFE） in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2.