一种用于SAR ADC开关电容比较器的失调消除技术

论文阐述了一种用于逐次逼近ADC开关电容比较器的失调消除技术。采用预放大加再生锁存的比较结构,基于0.18μm 1P5M CMOS工艺设计实现了一种伪差分比较器。通过采用前级预放大器输入失调消除技术以及低失调再生锁存技术进行设计,整个比较器的输入失调电压小于0.55mV。通过采用预放大加再生锁存的比较模式,整个比较器的功耗有效减小,不足0.09mW。在电源电压为1.8V、ADC采样速率为200kS/s、时钟频率为3MHz的情况下,比较器能达到13位的转换精度。最后,通过设计讨论、后仿真分析及其在一种10位200kS/s的触摸屏SAR ADC中的成功应用验证了本文比较器的实用性和优越性。     

A clocked high-pass-filter-based offset cancellation technique for high-gain biomedical amplifiers

In this article, a simple offset cancellation technique based on a clocked high-pass filter with extremely low output offset is presented. The configuration uses the on-resistance of a complementary metal oxide semiconductor (CMOS) transmission gate (X-gate) and tunes the lower 3-dB cut-off frequency with a matched pair of floating capacitors. The results compare favourably with the more complex auto-zeroing and chopper stabilisation techniques of offset cancellation in terms of power dissipation, component count and bandwidth, while reporting inferior output noise performance. The design is suitable for use in biomedical amplifier systems for applications such as ENG-recording. The system is simulated in Spectre Cadence 5.1.41 using 0.6 μm CMOS technology and the total block gain is ～83.0 dB while the phase error is <5°. The power consumption is 10.2 mW and the output offset obtained for an input monotone signal of 5 μVpp is 1.28 μV. The input-referred root mean square noise voltage between 1 and 5 kHz is 26.32 nV/√Hz.     

Technique for offset voltage cancellation in MOS operational amplifiers

A novel technique for the continuous-time removal of the input offset voltage in operational amplifiers is presented. This scheme converts a conventional op-amp into a similar differential-in/differential-out op-amp with zero differential input offset voltage. The nonzero common-mode input offset voltage can be isolated using a sampled-data time-averaging technique and minimised by negative feedback.     

A co-channel interference cancellation technique using orthogonalconvolutional codes

This paper proposes a new parallel co-channel interference cancellation technique which utilizes orthogonal convolutional codes. Co-channel interference (CCI) limits the performance of a spread spectrum multiple access communication link. Several CCI cancellation techniques have been proposed to remove this interference. Of particular interest are techniques which do not require the receiver to have knowledge of the cross-correlation between user sequences. These techniques reconstruct the CCI based on the initial decisions regarding the signals from the other users. However, these techniques leave residual interference after cancellation caused by errors in these initial decisions. To improve the initial decisions and reduce the residual interference, our proposed scheme utilizes the error correcting capability of orthogonal convolutional codes. This paper evaluates the performance of this scheme. We show that, given a processing gain of 128 for up to about 40 users, the performance of the proposed CCI canceller approaches the performance of a system without multi-user interference. We also show that the proposed CCI canceller offers an improvement in capacity by a factor of 1.5~3 over that of a conventional canceller     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed in this paper. The proposed VGA uses the differential-ramp based technique, digitally programmable gain amplifier (PGA) can be converted to analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous time feedback that includes Miller effect and linear rang operation MOS transistor to realize large value capacitor and resistor to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in SMIC 0.13 m CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58mm2 of chip area including bondpads. In addition, the DCOC circuit shows 500Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

Optimisation of direct auto-zeroing offset cancellation in low voltage applications using dual level CMFB

A modified CMFB circuit is presented that reinstates the use of direct opamp auto-zeroing offset cancellation techniques in low voltage applications. This approach is particularly useful for high precision sample and hold amplifiers and Nyquist rate ADCs, where the opamp is reset during one of the clock phases. Differential offsets up to 50 mV are effectively reduced as demonstrated by a sample and hold example.     

An automatic error cancellation technique for higher accuracy A/D converters

An automatic error cancellation technique for higher accuracy successive-approximation analog/digital (A/D) converters is described. The technique uses a binary-weighted capacitor array as its own reference, and no other special elements are required for capacitor mismatch compensation. Experimental results indicate that more than 14-bit A/D conversion can be performed on a conventional MOS IC chip without trimming.     

A feedforward excess-phase cancellation technique for integrators

Integrators are useful analogue function blocks. A representative application of integrators is a continuous-time filter on an integrated circuit. Excess phase shift of integrators is one of the most severe problems, because excess phase shift at the unity gain frequency degrades the frequency characteristics of the filters. This paper describes a feedforward excess-phase cancellation technique. The proposed technique is applied to integrators which have feedback with an amplifier. The proposed idea is verified by experiment. It is shown that the excess-phase shift due to the gain-bandwidth product of operational amplifiers is cancelled. The proposed technique is useful for realization of integrated continuous-time filters using integrators because extra capacitors are unnecessary. An integrator with the excess-phase cancellation and a third-order leapfrog filter using the integrator are designed and demonstrated by HSPICE simulation. The integrator has a parasitic pole whose frequency is proportional to the unity gain frequency. The simulation results show that the phase characteristics are improved by the proposed technique over the wide range of the unity gain frequency.     

An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs

The input referred offset voltage occurring in the full latch V/sub DD/ biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by /spl plusmn/2.5% variation in V/sub T/ and /spl plusmn/5% variation in /spl beta/, from typical values. Effect of various design parameters on the sense amplifier offset has been studied and reported. It has been shown that the rise time of the sense amplifier enable signal (SAEN) has a profound effect on the offset voltage. The slower transition of SAEN signal is proposed to result in high speed as well as low-power consumption in SRAM application. An analytical model has been derived for simplified latch to model the effect of rise time of SAEN signal on offset voltage.     

A finite-mesh technique for laser trimming of thin-film resistors

A laser trimming technique in which a finite number of links are cut in a regular mesh of identical-valued resistors is described. The method eliminates long-term resistance drift due to slow annealing in the `heat-affected-zone' adjacent to the laser kerf. It is shown that the precision and resolution can be comparable to those achieved with conventional methods, and that quite wide ranges (up to 4:1) of absolute values can be obtained with small meshes. A computational method for constructing a lookup table of resistor values for different cut patterns is described     

Efficient ISI cancellation for STBC OFDM systems using successive interference cancellation

In this letter, we propose an efficient detection scheme for space-time block coded (STBC) orthogonal frequency-division multiplexing (OFDM) with insufficient cyclic prefix (CP). The proposed scheme employs successive interference cancellation (SIC) and cyclic prefix reconstruction (CPR) concepts. Simulation results present that the proposed scheme outperforms the conventional scheme for STBC OFDM systems.     

Flicker noise cancellation technique for low-voltage direct-conversion mixers

A technique to reduce the low-frequency noise figure of direct-conversion mixers is presented. Unlike previous techniques, the proposed method is suitable for low-voltage and low-power applications. The results presented demonstrate that the proposed technique can significantly improve the low-frequency noise figure of the mixer, while other performance parameters remain intact.     

An efficient technique for the computation of vector secondary patterns of offset paraboloid reflectors

A series approach for the rapid computation of the vector secondary pattern of offset paraboloid reflectors wherein the feed is displaced is presented. We show that the Jacobi polynomial series method, which has been demonstrated to provide an efficient means for evaluating the radiation integral of symmetric paraboloid reflectors, can be extended to the case of an offset paraboloid without compromising the ease or speed of computation. The analysis leading to the series formula is also useful for deriving an analytic expression for the optimum scan plane for the displacement of the feed. Representative numerical results illustrating the application of the method and the properties of the offset paraboloid are presented.     

一种适用于传感器接口电路中电容型SAR结构ADC的修调技术

本文提出了一种针对电容型逐次逼近型模数转换器（ADC）的修调技术及实现算法,采用了该技术的ADC可作为传感器和微控制器之间的接口电路使用。其特点在于这种修调后的电路可以在不需要单独的校正周期,也不需要附加复杂的校正功能,只需要通过对电容阵列的微调,就可以达到12-bit的分辨率。这种技术具有功耗和面积的优势,适合用于对功耗和成本较为敏感的电池供电系统,例如传感器网络结点。本文在0.5μm 2P3M CMOS工艺下设计了一个12bit分辨率的ADC原型电路,在2-5V电源电压下,200KHz采样速度下,其功耗仅为300μA。     

A predistortion linearizer using envelope-feedback technique withsimplified carrier cancellation scheme for class-A and class-AB poweramplifiers

A predistortion linearization method using an envelope-feedback technique is proposed and implemented in this paper. This linearizer compensates the gain and phase nonlinearity of power amplifier (PA) simultaneously by controlling both variable attenuator and phase shifter with the feedback of only the difference signal between input and output envelopes. A new carrier cancellation scheme composed of a minimization circuit, log detector, and vector modulator is also presented. This circuit achieves adaptive control of the linearizer by enabling direct measurement of out-of-band power. It is well suited to a multichannel system where the allocated channels are time variant. The principle of the proposed linearizer is described and simple AM-AM distortion analysis is presented analytically and graphically based on the conceptual schematic diagram. A two-tone test for a class-A PA at 1.855 GHz with frequency spacing of 1 MHz showed intermodulation-distortion reduction of maximum 16 dB and stable operation over 5-dB output power variation up to 4-dB backoff from the saturation power level. The proposed linearizer is also applicable to class-AB PA's without further special adjustments. The adaptation circuit is fully implemented with analog integrated circuits, which can further extend its applicability with the integration technology     

Single-mode-fibre cutoff measurements using offset splice technique: excess loss effects

The effect of excess loss mechanisms on the measurement of the LP11 mode cutoff wavelength using the offset splice technique is investigated. We show that the measured cutoff wavelength will shift towards shorter wavelengths only if excess attenuation is present in both the emitting and receiving fibres. The shift is not observed if the excess loss is only present in one of the two fibres.     

A frequency offset estimation technique for frequency-selectivefading channels

Rapid frequency offset estimation is required in burst communication systems. The performance of traditional open loop frequency estimation techniques is severely degraded by multipath propagation. We present a new data-aided technique for frequency offset estimation in the presence of strong multipath. The technique allows estimation of the frequency offset with no knowledge of the channel parameters. Results comparing the new technique with the maximum-likelihood estimation technique in a frequency selective Ricean fading environment are presented     

Transmitter leakage cancellation technique for CMOS SAW-less radio front-ends

Digital audio sensors have been used in microphone-embedded portable electronics. This paper shows a mixed-signal adaptive readout ASIC for digital audio sensor, which includes a programmable-gain-amplifier, a switched-capacitor sigma-delta modulator, digital signal processing, and power management circuits. The digital part comprises a digital low-pass filter, a digital-gain-compensation and a digital automatic-gain-controller. The clear advantage of this system is to obtain high signal-to-noise ratio (SNR) and wide input range simultaneously. In addition, both a normal operation mode and a sleep mode are realized to address a flexible current budget. The ASIC is fabricated in a 0.18-um CMOS process. Experimental results show the expected adaptive readout function over the input range from 94 to 136 dB SPL. In the normal mode, a system SNR of 68 dB (A-weighted) at 1 kHz 94 dB SPL input is achieved under 600 uA. Further, an impressive acoustic overload point (AOP) of 136 dB SPL is guaranteed. In the standby condition, the sleep mode with current less than 20 uA is obtained, so that the battery life can be extended. Compared to other existing solutions, this adaptive readout ASIC shows the best combination of achievable SNR, AOP and current budget for digital audio sensors.