A high frequency “divide-by-odd number” CMOS LC injection-locked frequency divider

Numerous circuit topologies have been proposed for divide-by-ρ injection-locked frequency dividers (ILFDs), most of which have been optimized for division by even numbers, especially divide-by-2. It has been more difficult to realize division by odd numbers, such as divide-by-3. In this paper we present simulations of an RF CMOS ILFD that can operate equally well in both divide-by-2 and divide-by-3 modes. The ILFD is based on a cross-coupled CMOS LC oscillator with direct injection and an auxiliary injection path. The paper presents two variants of the circuit architecture and Cadence simulations in the multi-GHz frequency range using a standard TSMC 65 nm CMOS process design kit.     

A 1.78–3.05?GHz fractional-N frequency synthesizer with power reduced multi-modulus divider

Nowadays, multi-band frequency synthesizers are very popular for their compatibility, which lowers the chip cost. In this article, a low power 2.4?GHz broadband fractional-N frequency synthesizer based on ???C?? modulation is presented. A novel power reduced multi-modulus divider based on 2/3 divider cells is presented. The ??mod?? signals are employed to dynamically control the current of the end-of-cycle logic blocks in 2/3 divider cells. When the end-of-cycle logic blocks have no contribution to the divider operation, they are turned off to save power. The saved power is more than 30% in the desired division ratio range. A dual-band voltage controlled oscillator with switched capacitor arrays is designed to cover a wide tuning range. Other circuits such as phase frequency detector, charge pump and loop filter are also integrated on the chip. The whole frequency synthesizer has been fabricated in Chartered 0.18???m RF CMOS process. Tested results show it covers the tuning range from 1.78 to 3.05?GHz, with phase noise smaller than ?85 dBc/Hz at 100?kHz offset, and smaller than ?115 dBc/Hz at 3?MHz offset. Its power consumption is only 9.2?mW under 1.8?V supply voltage, and the chip occupies an area of 1.2?mm?×?1.3?mm.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

A wide-locking range ÷3 injection-locked frequency divider using concurrent injection mechanisms

A new wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD uses two concurrent injection mechanisms with two independent push–push circuits to extend the locking range. It is realized with a cross-coupled n-core MOS LC-tank oscillator. The core power consumption of the ILFD core is 11.496 mW. The divider’s free-running oscillation frequency is tunable from 4.32 to 3.78 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm the maximum locking range is 3 GHz (25 %), from the incident frequency 10.5 to 13.5 GHz. The operation range is 3.6 GHz (30.76 %), from 9.9 to 13.5 GHz.     

A 220 GHz dynamic frequency divider in 0.5 μm InP DHBT technology

A high performance 3 inch 0.5 μ m InP DHBT technology with three interconnecting layers has been developed. The epitaxial layer structure and geometry parameters of the device were carefully studied to get the required performances. The 0.5×5 μm² InP DHBTs demonstrated f_t=350 GHz, f_max=532 GHz and BV_CEO=4.8 V, which were modeled using Agilent-HBT large signal model. As a benchmark circuit, a dynamic frequency divider operating from 110 to 220 GHz has been designed, fabricated and measured with this technology. The ultra-high-speed 0.5 μm InP DHBT technology offers a combination of ultra-high-speed and high breakdown voltage, which makes it an ideal candidate for next generation 100 GHz+mixed signal integrated circuits.     

A 5-GHz programmable frequency divider in 0.18-μM CMOS technology

A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler (DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm; the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

A 0.35 μm CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage-current feedback topology

This paper presents a new divide-by-2 quadrature injection-locked frequency divider (QILFD). The QILFD consists of a new transformer-coupled quadrature voltage controlled oscillator (QVCO) with the voltage-current feedback technique and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS QILFD has been implemented with the TSMC 0.35 μm CMOS technology and the core power consumption is 16.52 mW at the supply voltage of 2.2 V. The free-running frequency of the QILFD is tunable from 2.85 GHz to 3.07 GHz. At the input power of 0 dBm, the divide-by-2 operation range is from 5.48 GHz to 6.48 GHz. The phase deviation of free running quadrature output is about 0.53°.     

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process

With the rapid evolution of wireless communication technology,integrating various communication modes in a mobile terminal has become the popular trend.Because of this,multi-standard wireless technology is one of the hot spots in current research.This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications.High-speed divider-by-2 with traditional sourcecoupled-logic is designed for very wide band usage.Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step.The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider.△-Σ modulator is achieved by an improved MASH 1-1-1 structure.This structure has excellent performance in many ways,such as noise,spur and input dynamic range.Fabricated in TSMC 0.18 μm CMOS process,the fractional-N frequency divider occupies a chip area of 1130 × 510μm2 and it can correctly divide within the frequency range of 0.8-9 GHz.With 1.8 V supply voltage,its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.     

A 330?MHz 11?bit 26.4?mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is designed and experimental results are presented. The sample-and-hold circuit operates up to 330 MHz of sampling frequency with less than −68.3 dB of total harmonic distortion, corresponding to 11 bits for an input 80.24 MHz sinusoidal amplitude of 1.2V _pp at a 3 V supply. This total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.2 V step input, and 1.2V _pp full-scale differential input range are achieved. The circuit dissipates 26.4 mW with a 3 V power supply.     

A low-power differential injection-locked frequency divider with output power flatness in 0.5 μm E/D-mode GaAs PHEMT

This study implemented an injection-locked frequency divider (ILFD) on Ka-band millimeter-wave communication systems in 0.5 μm enhancement/depletion-mode (E/D-mode) GaAs PHEMT technology. The ILFD presents a low-power design based on the differential-injection circuit topology without using any injectors. Compared with the conventional single-injection ILFD circuits, the proposed ILFD exhibits output power flatness and wide locking range characteristics with a power consumption of 0.9 mW under a 0.4 V supply. The self-oscillation frequency was chosen to be 20 GHz for divided-by-2 operation. The measured locking range is approximately 11.5 GHz ranging from 32.5 GHz to 44 GHz when the injection power level is 5 dBm. The locking range exhibiting a 3 dB power roll-off characteristic at output is 10.5 GHz ranging from 33 GHz to 42.5 GHz.     

A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system

In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding–interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.     

A 8?mW 72?dB ΣΔ-modulator ADC with 2.4?MHz BW in 130?nm CMOS

A double-sampling split ????-ADC with bilinear integrators and a 7-level quantizer is presented. It achieves third order noise shaping with a second order modulator through quantization noise-coupling. The modulator is integrated in a 130?nm CMOS technology. For a clock frequency of 48?MHz and an oversampling ratio of 20 (2.4?MHz signal bandwidth), it achieves 72?dB DR and 68?dB SNR. The prototype consumes 8?mW from a 1.2?V voltage supply.     

A selectable-bandwidth 3.5 mW, 0.03?mm2 self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5?MHz and 65 dB at 10?MHz bandwidth

In this paper we present a dual-mode third-order continuous time $\Upsigma\Updelta$ modulator that combines noise-shaping and pulse-width-modulation (PWM). In our 0.18???m CMOS prototype chip the clock frequency equals 1?GHz, but the PWM carrier is only around 125?MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10?MHz. In the 5?MHz mode the peak SNDR equals 64?dB and the dynamic range 71?dB. In the 10?MHz mode the peak SNDR equals 58?dB and the DR 65?dB. This performance is achieved at an attractively low silicon area of 0.03?mm² and a power consumption of 3.5?mW.     

Weak-acceptor-polyacrylonitrile/donor-polyaniline core–shell nanofibers: A novel 1D polymeric heterojunction with high photoconductive properties

A novel one-dimensional (1D) polymeric heterojunction based on weak-acceptor-polyacrylonitrile/donor-polyaniline core–shell nanofibers is designed for photoconductive devices through electrospinning followed by solution polymerization. Such 1D heterojunction can not only provide the large phase-separated nano-interface for effective charges separation between the cores and shells, but also facilitate the mass charge collection and transport along the nanofiber structure, resulting in greatly enhanced optoelectronic performance. The short 0.1 s response time upon irradiation is among the fastest values, as is the short 0.1 s time for return to the non-irradiated state. Extremely high on–off resistivity ratios (exceeding 4 × 10⁴) can be obtained under the drive voltage of only 0.01 V, indicating the energy required for electrical input is very small. Higher drive voltages (a modest 10 V) can provide a very high responsivity of 20 A W⁻¹ driven by 365 nm UV irradiation. Moreover, the as-prepared flexible photoconductive device maintains performance even after bending fatigue tests for bending angles as large as 180°.     

A high performance 1 GHz voltage controlled oscillator using neural system architecture

In this paper, an improved voltage controlled oscillator scheme with temperature compensated frequency, a wide linear range, low phase noise and low power dissipation is presented for application in transmitting signals of gas sensors from mines using RF communication. The basic unit of the oscillator is a ring based differential amplifier incorporating temperature compensated voltage dependent PMOS capacitors and standard PMOS triode connected load with temperature compensated biasing scheme. The increased nonlinearity in the presence of PMOS capaciors is reduced to 0.001% using a digitally programmable neural architecture which is simulated in the mixed signal domain of SYNOPSYS. Additionally, the temperature compensated PMOS capacitor improves the sensitivity of the VCO and the standard temperature compensated biasing scheme of the PMOS triode connected load reduces the drift in amplitude with temperature variation. The PMOS varactor lowers the phase noise of the VCO compared to parasitic capacitors without increasing the power dissipation. The entire VCO is designed using 0.18 μm typical technology of TSMC with 1.8 V power supply. The tuning range of the VCO is 0.3–1.7 V, maximum frequency is 1 GHz with a linear change of around 750 MHz, temperature sensitivity and power consumption are around 50 ppm/°C and 2 mW respectively. The phase noise is obtained to be around −123dBc/Hz at 1 MHz offset frequency.     

A 22?mW 512?MHz CMOS continuous time sigma delta ADC in 1.2?V with 16?MHz signal bandwidth and 70?dB dynamic range

A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130?nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512?MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-to-zero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60?dB SNR and a 59.3?dB signal-to-noise-plus-distortion ratio over a 16?MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2?V supply.     

CISPR 14-1:2005与EN 55014-1:2000+A1+A2的主要差异及对测试的影响

以CISPR 14-1:2005为基础,与欧盟的EN 55014-1:2000 A1 A2相比较,找出其中主要差异以及差异导致的测试方法的改变,为测试机构和生产企业的产品测试和设计提供参考.