Over rail-to-rail fully differential voltage-to-current converters for nm scale CMOS technology

The converters presented in this paper are based on long channel complementary MOS transistors, instead of the commonly used differential amplifiers or differential transistor pairs which are difficult to implement in low voltage, nm scale CMOS technology. Nonlinearities of drain currents can be cancelled in the fully differential structure. As a result, the low power, nanometre standard digital CMOS technology converters are obtained. Layout examples are designed in 65 nm TSMC technology. Post-layout simulations show that the range of input voltage over rail-to-rail is achieved with very good linearity and reduced harmonic distortion.     

Sensorless current mode control-an observer-based technique forDC-DC converters

Sensorless current mode (SCM) control is an observer method that provides the operating benefits of current mode control without current sensing. SCM has significant advantages over both conventional peak and average current-mode control techniques in noise susceptibility and dynamic range in both continuous mode and discontinuous mode. The method supports line and bulk load regulation, and reduces control complexity to a single loop. It also supports conventional two-loop control for tight load regulation. Encompassing one-cycle control as a special case, the general SCM method is a public domain control technique     

Circuit technique for wide-range, linear, voltage-to-current convertors

A `current-balancing? circuit technique, involving the use of an emitter-follower and two complementary current mirrors, facilitates the design of a voltage-to-current convertor in which the input voltage control range extends down to within a few tens of millivolts of earth potential despite the use of a single system rail supply.     

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as g_m-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than ? 9.58 dB while output return loss has less than ? 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm².

     

A simple input current wave-shaping technique for three-phase diode and SCR converters

Three-phase converters using diode or silicon-controlled rectifier (SCR) are widely employed to convert the commercial AC supply to DC. Such converters inject harmonics into the power supply system and thereby distort supply system voltage waveform. A simple input current wave-shape improvement technique using a shunt-connected harmonic current compensator is presented in this work, intended to reduce the total harmonic distortion (THD) of input current of three-phase diode and SCR phase-controlled rectifiers operating with inductive loads, by matching them to the specific converter as a combined package. The compensator proposed here comprises of a three-limb voltage source converter using insulated-gate bipolar transistor, working on instantaneous current and voltage measurements of the compensator only and not of the load. The technique uses a simple feedforward control for AC source current harmonic compensation of rectifiers without monitoring the AC line currents, i.e. use of online computation. The proposed system is simulated and tested on a laboratory prototype. The measured input current THD values without additional line filters are found to be below 8.3%, which is within acceptable limits, proving that the new technique is capable of compensating predetermined current harmonics of diode or SCRs.     

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

Estimative current mode control technique for DC-DC converters operating in discontinuous conduction mode

A new control technique for DC-DC converters is introduced and applied to a boost converter operating in discontinuous conduction mode (DCM). In contrast to conventional control methods, the principal idea of the proposed control scheme is to obtain samples of the required signals and estimate the required switch-on time. The proposed technique is applicable to any converter operating in DCM, including power factor correctors (PFC), however, this letter mainly focuses on boost topology. In this letter, the main mathematical concept of a new control algorithm is introduced, as well as the robustness investigation of the proposed method with simulation and experimental results.     

Linear multiloop control of quasi-resonant converters

The aim of this paper is to study the stability of linear multiloop control of quasiresonant converters (QRC). It is shown that a P-current feedback, plus an I-voltage feedback suffices to stabilize a QRC. A systematic procedure of control synthesis is presented and stability conditions for the control parameters are derived from nonlinear systems theory. Performance of the proposed controller is verified through an experimental application in a boost type QRC.     

Novel nonlinearity minimized time-to-digital converters with digital calibration technique

Analog Integrated Circuits and Signal Processing - This paper presents a low nonlinearity, four channel Gated Ring Oscillator (GRO) based Time-to-Digital Converters (TDC) in Xilinx 28 nm...     

Efficient current reuse for low-power transceivers

Current boosting is a method where the performance of an active circuit block is optimized by placing a constant current source in parallel with the active signal path to provide optimal biasing for different components. In this paper, a technique to replace the constant dc current source with active building blocks typically required in transceivers is proposed. By using this method the total current consumption of the transceiver can be efficiently reduced without modifying its performance. A design example where the proposed technique reduces the receiver current consumption by 45% is given.     

Calibration technique for SAR analog-to-digital converters

A self-calibration technique was developed for SAR analog-to-digital converters that employ binary-weighted capacitors. High-accuracy calibration is achieved by finding and correcting the mismatch of each capacitor independently. The mismatch errors are extracted at power-up, and corrected by individual calibration DACs during the conversion. Unlike in previous schemes, in the proposed method the residual error in the calibration of a capacitor does not affect the calibration of any other capacitor. Simulation results show that the proposed method is also insensitive to the non-idealities of the calibration DACs.     

Variable-gain up-converter with current reuse for 5-GHz WLAN applications

A variable-gain up-conversion mixer for 5-GHz WLAN applications is presented, whose input stage is based on a novel variable gain transconductor. The proposed topology features reduced power consumption by exploiting dc current reuse for mixer biasing. Moreover, a new low-consumption control circuit is introduced, which achieves a temperature-stable and linear-in-dB characteristic, providing a 40-dB dynamic range within ±1 dB gain error.     

Averaging technique in flash analog-to-digital converters

The averaging technique is used in flash analog-to-digital converters to reduce nonlinearities resulting from random offset voltages of the pre-amplifiers, which stand before the comparators. The main contribution of this paper is to provide further insight into this technique, through exact closed-form expressions obtained for the output voltage, gain, integral nonlinearity and differential nonlinearity in averaged pre-amplifiers. These theoretical results are compared with HSPICE simulations, and a very good agreement is found. Finally an automatic design procedure is described, which is based on the expressions derived, and a design example is given.     

ARCP soft-switching technique in matrix converters

An alternative concept used to avoid the need for staggered switching in matrix converters is discussed. The features of the auxiliary resonant commutated pole (ARCP) soft switching technique are used to reduce the number of active switches and gate drives in comparison to conventional matrix converter technology, avoid commutation voltage spikes, and reduce switching losses. Three different ARCP matrix converters are reviewed and their operational boundaries are discussed. The ARCPMC technology is critically evaluated with respect to a potential industrial application     

Switching technique for current-controlled AC-to-AC converters

The AC-to-AC converter called the matrix converter is very simple in structure and has powerful controllability. However, there are few practical applications, particularly in power electronics fields. The major reasons largely lie in the commutation problem and complexity of the control circuit. This paper proposes a novel commutation technique which is very simple to implement. This commutation scheme allows the deadtime to avoid current spikes of nonideal switches and, at the same time, establishes a current path of the inductive load to avoid voltage spikes. A switching technique of the matrix converter using a space-vector-modulation (SVM) based hysteresis current controller (HCC) is also proposed. The switching technique is implemented without any computational burden and is controlled with a simple control circuit. This technique utilizes advantages of the HCC and SVM technique. Simulation and experimental results obtained on a 5 kW single-phase AC chopper and an 11 kW three-phase to three-phase matrix converter are discussed     

Switched link PWM current source converters with harmonicelimination at the mains

Novel switched link pulse-width-modulated (PWM) current source converters are presented. These converters supply a controlled DC current to the load with a concurrent elimination of selected harmonics in the AC mains. The new topologies permit minimal constraints to be formulated resulting in significantly more efficient PWM patterns than hitherto reported in the literature. A higher number of harmonics are thus eliminated at the mains for a given switching frequency while maintaining a control capability of the output DC current in a wide range. Simulation results confirm the theoretical findings. Also discussed in the paper is the selection of capacitor filters to mitigate the residual harmonics     

Feedforward current control of boost single-phase PFC converters

This paper presents the theory and application of feedforward current control for boost single-phase ac-dc converters with power factor correction. The proposed feedforward signal involves the instantaneous line voltage and the derivative of the reference current. The new control method is compared to existing feedback and feedforward control methods and is shown to significantly reduce input current harmonic distortion, particularly for applications where the current loop crossover frequency is relatively low compared to the line frequency. Implementation of the proposed control using analog devices and the associated issues, such as performance sensitivity to parameter variation and uncertainties, are presented. Analysis results are complemented by numerical simulation and experimental results from a prototype converter. Targeted applications of the proposed method are airborne systems where the line frequency is high, as well as low-cost digital control for terrestrial 50-60-Hz systems where the current loop crossover frequency is limited by the speed of the digital controller.     

高功率密度系统需要大电流转换器

本文介绍了降压型稳压器设计中需要注意的问题及面临的新挑战,并介绍了LTC7150S和LTC7130两款满足特定需求的降压型变压器.     

BiCMOS current cell and switch for digital-to-analog converters

A BiCMOS current cell and current switch used in a current steering DAC are proposed. The BiCMOS self-calibrated current cell offers higher output resistance and smaller minimum voltage and shows up to a factor of 2 improvement in accuracy in simulations. The BiCMOS current switch has no base current error and achieves close to a factor of 2 improvement in simulated switching speed when compared to a MOS switch