Analog sigma–delta modulation with Op-Amp gain compensation for nanometer technologies

A new method that compensates for low DC gain in operational amplifiers (Op-Amps) used in discrete time $\Sigma\Delta$ Σ Δ modulators is described. Measuring and buffering the error at the Op-Amps inverting terminals enables a complete cancellation of the phase error. Nanometer Op-Amps that achieve low gain but very high bandwidth become usable at oversampling rates that still present DC gain limitation. Simulations at behavioral and 65 nm CMOS transistor level implementation verify the effectiveness of the proposed technique.     

Excess loop delay cancellation in sigma–delta modulators

Excess loop delay in sigma–delta ( $\Sigma\Delta$ ) modulators, especially by increasing the level of noise in signal bandwidth in continuous kind of them, leads to a dramatic decrease in their efficiency. In this paper, the error originated from the loop delay is calculated analytically and a new structure for sigma–delta modulators is presented based upon this calculation. This new structure can compensate the effect of loop-delay error completely independent of amount of delay. So by changing in loop delay during system working, the proposed structure has ability to consistent itself with new conditions and re-eliminate the error. This ability is independent of being multi-bit and the order of modulator. To evaluate the efficiency of the proposed method and the corresponding structure, first and second order modulators with capability of eliminating the error of loop delay, have been designed and simulated. All of simulations show the correctness of proposed analysis. Comparison of the proposed structures with the previous works shows the effectiveness of our technique.     

A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18 μm CMOS process. The measurement results show that the random noise (RN) is 7e_rms⁻, the pixel conversion gain is 100 μV/e⁻. Since the measured full well capacity of the pixel is 25000e⁻, the CMOS image sensor achieves a 71 dB dynamic range (DR). The total power consumption at 60frame/s is 58.2 mW.     

Systematic approach to the synthesis of continuous-time cascaded sigma–delta modulators

This paper deals with a systematic approach to the synthesis of continuous-time cascaded sigma–delta modulators. Based on a system-theoretical model, a detailed derivation of the digital cancelation filters for continuous-time cascaded architectures is presented in order to achieve maximum signal-to-noise ratio together with optimal anti-aliasing performance. By using the same model, an exact equation for the performance loss of any cascaded architecture is derived. The latter is due to the scaling for stability and given relative to an ideal high-pass filter of the overall modulator order. Finally, an analytical calculation of optimal scaling coefficients in between the stages is performed, resulting in a limited search-space for these coefficients. Theoretical results are verified by simulations.     

Reliability aware design of low power continuous-time sigma–delta modulator

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.     

Implementation of THD-reduction stereo audio amplifier using compensators and sigma–delta modulators

This paper presents an integrated stereo audio amplifier that employs sigma?Cdelta (????) modulation techniques with compensators. Traditional closed-loop audio amplifiers adopt pulse-width modulation or ???? modulation techniques. The design method proposed in this study uses a negative feedback closed-loop system with compensator and ???? modulator. This combination of compensator and ???? modulator significantly reduces the noise and total harmonic distortion (THD) compared with a traditional closed-loop system. The proposed negative feedback loop can automatically compensate for external perturbations, improving the precision of the eventual output. The compensator increases the audio-frequency loop gain, and leads to better rejection of audio-frequency disturbances. At a sample rate of 10?MHz, the proposed audio amplifier achieves 0.04% THD and a signal to noise ratio of 87?dB with efficiency above 92%. The proposed audio amplifier was implemented in a TSMC 3.3?V 0.35???m 2P4M CMOS process.     

Enhanced split-architecture delta–sigma ADCs

A split delta–sigma ADC topology is proposed, which provides enhanced noise shaping by cross-coupling the quantization errors of the two halves of the structure. Unlike the multi-stage noise shaping (MASH) architecture, the new structure is insensitive to mismatch errors, and it does not reduce the stability of the loops. Simulations confirm the effectiveness of the proposed scheme.     

Robust feedforward compensation scheme with AC booster for high frequency low voltage buck DC–DC converters

Today and in the future, high frequency low voltage DC–DC converters are an effective power-management solution for fast transient response and small profile in portable electronic systems. This paper presents a robust feedforward compensation scheme with AC booster. An ac amplifier is added in parallel with the main path to compensate the high-frequency gain reduction, which improves gain-bandwidth (GBW) product and slew rate significantly. This approach takes the multistage error amplifier (EA) as an element in the compensation circuit instead of using passive elements used in traditional proportional-plus-integral-and-derivative (PID) compensation circuits. The positive phase shift of left-half-phase (LHP) zeros caused by the feedforward path and ac boosting path in the multistage EA is used to cancel the negative phase shift by the resonant poles of the power stage of buck DC–DC converter in order to compensate the DC–DC converters. A graphical loop-gain method is used to design the feedback compensation and analyze the closed-loop performances of the converter for the complexion arising from the presence of multiple poles of EA before crossover frequency in high frequency converters. The high gain, wide bandwidth, and high slew rate are achieved by the absence of traditional pole-splitting effect and the added ac booster. In addition, the design guidelines for this feedback compensation network realized by robust feedforward with AC booster compensation (RFACBC) scheme and multistage EA are established. When the proposed compensation networks were employed in 100 MHz buck DC–DC converter implemented in SMIC 0.18 μm CMOS process, the simulation results validate the feasibility and functionality of the RFACBC scheme and design guidelines. The closed-loop dc gain achieves over 60 dB with over 20 MHz GBW and 61° phase margin under wide range loads. Furthermore, the settling time is improved due to the advanced frequency compensation.     

Low-clock-speed time-interleaved architecture for a polar delta–sigma modulator transmitter

The polar delta–sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software-defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low-complexity time-interleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four-branch time-interleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal-to-noise-and-distortion ratio.     

A sigma–delta interface ASIC for force-feedback micromachined capacitive accelerometer

A single-loop fourth-order sigma?Cdelta (????) interface circuit for micromachined accelerometer is presented in this study. Two additional electronic integrators are cascaded with the micromachine sensing element to form a fourth-order loop filter to eliminate quantization noise. A precise model for the overall system is set up based on nonlinear model of 1-bit quantizer. Three main noise sources affecting the overall system resolution of a ???? accelerometer: mechanical noise, electronic noise and quantization noise are analyzed in more detail. A switched-capacitor charge integrator and correlated double sampling are applied to reduce input-referred electronic noise. The ASIC is fabricated in 0.5???m two-metal two-poly n-well CMOS process, and test results show that the noise density floors of the open-loop and closed-loop modes are 12 and 80???g/Hz^1/2, respectively, the sensitivity is 1.25?V/g, the full measurement range can be achieved from ?2 to +2?g, and the power dissipation is 40?mW.     

A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators

Excess loop delay is one of the most critical non-idealities of continuous-time delta–sigma modulators as it leads to degradation of the signal-to-noise-ratio or even instability. A comprehensive study of the impact of excess loop delay on tunable continuous-time bandpass delta–sigma modulators using RC-resonators is performed in this paper, both analytically and by simulations. Moreover, a detailed analysis of the conventional compensation techniques for single-band continuous-time bandpass modulators as well as their adaptability to tunable bandpass modulators is performed. The results indicate that only tuning of the scaling coefficients is suitable to compensate for excess loop delay in high-speed tunable bandpass modulators. Based on this result, an approach to the compensation of excess loop delay is proposed which maps the poles of the noise transfer function (NFT) to almost ideal and thus stable positions. Excess loop delay equal to one clock cycle may thus be compensated while the available tuning range of the center frequency depends on the order and the out-of-band-gain of the NFT. A prototype implemented on a printed circuit board proves the feasibility of the proposed approach.     

A 0.8-V 816-nW delta–sigma modulator for low-power biomedical applications

This letter discusses the implementation of a low-voltage, low-power delta–sigma modulator as a sensing stage for biomedical applications. A distributed feed-forward structure and bulk-driven operational transconductance amplifier are used in order to achieve efficient operation at a supply voltage of 0.8 V. Instead of conventional low-voltage amplifier architectures, our design uses folded-cascode amplifiers, although they are not used in most low-voltage circuits. A wide input swing is achieved by using the bulk-driven approach, and the drawback of the limited voltage swing of the cascoded output stage is overcome by the distributed feed-forward modulator. The designed modulator has a dynamic range of 49 dB at a 0.8-V supply voltage and consumes only 816 nW of power for the 250-Hz bandwidth. The core chip size of the modulator is 1000 μm × 500 μm by using the 0.18-μm standard CMOS process.     

Reconfigurable bandpass sigma–delta modulator with programmable NTF for low-IF multi-mode receivers

A new reconfigurable bandpass sigma–delta modulator (BPSDM) structure is proposed for low-IF multi-mode wireless systems. The proposed modulator can be reconfigured to operate in different signal bandwidths and at different signal-to-noise ratios by rearranging and optimizing the order of the noise transfer function of the loop while still maintaining stability. Compared with conventional multi-mode BPSDM, employing cascade structures and multi-bit sub-ADCs, the proposed modulator features many attractive advantages, such as (1) avoiding coefficient mismatch between analog and digital components in cascade structures, (2) avoiding DAC non-linearities that are otherwise introduced by commonly used dynamic element matching techniques, and (3) improving and varying the dynamic range performance while meeting the requirements of different wireless standards.     

A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

A low-distortion feed-forward MASH2_4b-2_4b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18 μm CMOS process with single 1.8 V supply voltage, the converter achieves a peak SNDR of 85.4 dB over a 10 MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94 dB for a 1.25 MHz@–6dBFS input signal at 160 MHz sampling frequency. The occupied area is 0.44 mm² and dissipation power 23.4 mW.     

Extended frequency-band-decomposition sigma–delta A/D converter

Parallelism can be used to increase the bandwidths of ADC converters based on sigma–delta modulators. Each modulator converts a part of the input signal band and is followed by a digital filter. Unfortunately, solutions using bandpass sigma–delta modulators are very sensitive to the position of the modulators’ central frequencies. This paper shows the feasibility of a frequency-band-decomposition (FBD) ADC using continuous time bandpass sigma–delta modulators, even in the case of large analog mismatches. The major benefit of such a solution, called extended-frequency-band-decomposition (EFBD) is its low sensitivity to analog parameters. For example, a relative error in the central frequencies of 4% can be accepted without significant degradation in the performance (other published FBD ADCs require a precision of the central frequencies better than 0.1%). This paper will focus on the performance which can be reached with this system, and the architecture of the digital part. The quantization of coefficients and operators will be addressed. It will be shown that a 14 bit resolution can be theoretically reached using 10 sixth-order bandpass modulators at a sampling frequency of 800 MHz which results in a bandwidth of 80 MHz centered around 200 MHz (the resolution depends on the effective quality factor of the filters of the analog modulators).     

A single-electrode capacitive sensor using incremental delta–sigma architecture

This paper presents a single-electrode capacitive sensor using a single-bit second-order incremental delta–sigma architecture. In order to achieve high accuracy in this capacitance-to-digital converter (CDC), the shielding signal and the digitally controlled offset capacitors are used in combination with the delta–sigma CDC. The designed sensor is suitable for capacitive transducers for ±10 pF input range with sub-fF resolution.     

A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 250 mV start-up voltage

A low voltage start-up energy harvesting medium frequency receiver is presented, for use as the power and synchronisation part of a remote sensor node in a wide area industrial or agricultural application. The use of embedded low bandwidth network synchronisation data permits very low operational duty cycle without the need for real time clocks or wake up receivers at each node with their associated continuous power drain. The receiver consists of a rectifier, a power management unit and a phase-shift keying demodulator. The rectifier is optimised for low start-up and operating voltage rather than power efficiency. With standard MOS thresholds the rectifier can cold start with only 250 mV peak antenna input, and useful battery charging is delivered with 330 mV peak input. The QPSK demodulator consumes 1.27 μW with a supply voltage of 630 mV at a data rate of 1.6 kbps with 1 MHz carrier frequency. The IC is implemented in a standard threshold 0.18 μm CMOS technology, occupies 0.54 mm² and can deliver 10.3 μW at 3 V to an external battery or capacitor.     

Analysis of high voltage step-up nonisolated DC–DC boost converters

A high voltage step-up nonisolated DC–DC converter based on coupled inductors suitable to photovoltaic (PV) systems applications is proposed in this paper. Considering that numerous approaches exist to extend the voltage conversion ratio of DC–DC converters that do not use transformers, a detailed comparison is also presented among the proposed converter and other popular topologies such as the conventional boost converter and the quadratic boost converter. The qualitative analysis of the coupled-inductor-based topology is developed so that a design procedure can be obtained, from which an experimental prototype is implemented to validate the theoretical assumptions.