共查询到20条相似文献,搜索用时 31 毫秒
1.
A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power 相似文献
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Mun-Kyu Choi Byung-Gil Jeon Nakwon Jang Byung-Jun Min Yoon-Jong Song Sung-Yung Lee Hyun-Ho Kim Dong-Jin Jung Heung-Jin Joo Kinam Kim 《Solid-State Circuits, IEEE Journal of》2002,37(11):1472-1478
Nonvolatile 32-Mb ferroelectric random access memory (FRAM) with-a 0.25-/spl mu/m design rule was developed by using an address transition detector (ATD) control scheme for the application to SRAM and applying a common plate folded bit-line cell scheme with current forcing latch sense amplifier (CFLSA) for increasing sensing margin, and adopting a dual bit-line reference voltage generator (DBRVG) for high noise immunity. Compared to a conventional FRAM device, the total chip size is reduced by 10.87%, which was achieved by using a single section data line (SSDL) and removing large gate-oxide capacitors, which is typically used for reference voltage generator for 1T1C FRAM. Furthermore, the imbalance of reference bit-line capacitance and main bit-line capacitance was resolved by using the CFLSA technique. 相似文献
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高速低功耗电流型灵敏放大器的设计 总被引:1,自引:0,他引:1
提出了一款适合在低电压、大容量SRAM中应用的高速低功耗电流型灵敏放大器。该电路在交叉耦合反相器之间添加了一对隔离管,有效消除了大量位线寄生电容所带来的负面影响,从而极大提高了灵敏放大器的速度。同时,通过对时序控制电路的优化,有效降低了放大器的功耗。采用SMIC0.13μm数字工艺在HSpice下进行仿真,结果表明:在室温,1.2V工作电压下,灵敏放大器的放大延迟仅为0.344ns,功耗为102μw。相比文献中提出的电流型灵敏放大器,速度分别提高了9.47%和31.2%,功耗则降低了64.8%与63%。 相似文献
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A significant improvement in sensing speed over the half-V DD bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V DD. The 2/3-V DD sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V DD sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V DD sensing with a limited bit-line swing has several distinct advantages over the half-V DD sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs 相似文献
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A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each corresponding to two-bit-data storage in a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier using charge coupling and charge sharing was developed for the four-level sensing and restoring. The sense amplifier uses a hierarchical bit-line scheme and operates in a time-sharing mode, thus reducing the sense amplifier area. A 4-Gb DRAM fabricated using 0.15-μm CMOS technology measures 986 mm2. The memory cell is 0.23 μm2. Its capacitance of 60 fF is achieved by using a high-dielectric-constant material BST 相似文献
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Matsumiya M. Kawashima S. Sakata M. Ookura M. Miyabo T. Koga T. Itabashi K. Mizutani K. Shimada H. Suzuki N. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1497-1503
Circuit techniques for a reduced-voltage-amplitude data bus, fast access 16-Mb CMOS SRAM are described. An interdigitated bit-line architecture reduces data bus line length, thus minimizing bus capacitance. A hierarchical sense amplifier consists of 32 local sense amplifiers and a current sense amplifier. The current sense amplifier is used to reduce the data bus voltage amplitude and the sensing of the 16-b data bus signals in parallel. Access time of 15 ns and an active power of 165 mW were achieved in a 16-Mb CMOS SRAM. A split-word-line layout memory cell with double-gate pMOS thin-film transistors (TFTs) keeps the transistor width stable while providing high-stability memory cell characteristics. The double-gate pMOS TFT also increases cell-storage node capacitance and soft-error immunity 相似文献
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Discusses the measurement of the minimum sense signal necessary for proper operation of the dynamic RAM (DRAM) sense amplifier. The minimum sense signal has been investigated experimentally by using a test structure that is basically a modified cross-coupled sense amplifier with 16-Mb DRAM feature sizes. Measured 5 sigma values of 27 mV correspond to variation in gate length, whereas 10 mV is found for bit-line capacitance asymmetries. The way that the minimum sense signal is affected by the different trigger-pulse slopes was investigated. A simple but illustrative analysis of the effect of device mismatches is developed and the measured values are compared with theoretical limits.<> 相似文献
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The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access 相似文献
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Watanabe S. Sakui K. Fuse T. Hara T. Aritome S. Hieda K. 《Solid-State Circuits, IEEE Journal of》1993,28(1):4-9
A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed 相似文献
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Nagai T. Numata K. Ogihara M. Shimizu M. Imai K. Hara T. Yoshida M. Saito Y. Asao Y. Sawada S. Fujii S. 《Solid-State Circuits, IEEE Journal of》1991,26(11):1538-1543
A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported 相似文献
13.
Taguchi M. Tomita H. Uchida T. Ohnishi Y. Sato K. Ema T. Higashitani M. Yabu T. 《Solid-State Circuits, IEEE Journal of》1991,26(11):1493-1497
The authors describe circuit techniques for wide input/output (I/O) data path and high-speed 64-Mb dynamic RAMs (DRAMs). A hierarchical data bus structure using double-level metallization has been developed to form 64-b parallel data bus lines without increasing the chip size. A current-sensing data bus amplifier, developed to sense the 64-b data bus signal in parallel, has made the wide I/O data path structure possible. A direct-sensing type column gate circuit with the READ/WRITE separated select line scheme achieves 40-ns RAS access. A shielded bit-line three-dimensional stacked-capacitor cell with a double-fin storage capacitor stores sufficient charge while the bit-line capacitance shows a reasonable value for sensing the data 相似文献
14.
Kim D.J. Ko J.H. Cho C.H. Park Y.I. Kang D.W. Min K.S. Kim D.M. Lee S.J. Shin H.S. 《Electronics letters》2003,39(16):1166-1167
Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations. 相似文献
15.
This paper describes a new bit-line sensing scheme that minimizes the sensitivity degradation caused by the electrical imbalance in a sense amplifier composed of scaled-down transistors. The new sensing scheme incorporates an offset compensating technique in a direct bit-line sensing scheme using a current-mirror differential amplifier. The compensation is performed by means of a simple negative feedback method that accomplishes cancellation of the total electrical imbalance in the sense amplifier with a short presetting time. The features of the circuit have been examined using simple DRAM test chips fabricated with a 0.5 μm CMOS process. Experimental results indicate that the magnitude of the imbalance of the sense amplifier is reduced to one-sixth by introducing the offset compensating scheme as compared to the conventional sensing scheme 相似文献
16.
Sarpeshkar R. Wyatt J.L. Jr. Lu N.C. Gerber P.D. 《Solid-State Circuits, IEEE Journal of》1991,26(10):1413-1422
Derives a new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in dynamic-RAMs (DRAMs), to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bit-line load capacitance mismatch. The formula yields insight into the DRAM sensing operation. The authors derive a sensitivity formula for this sensing scheme, using perturbation theory. The perturbation approach is rigorous: it avoids most approximations and ad-hoc assumptions, it introduces no free constants to be determined from simulations, and it yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design 相似文献
17.
Ogiwara R. Tanaka S. Itoh Y. Miyakawa T. Takeuchi Y. Doumae S.M. Takenaka H. Kunishima I. Shuto S. Hidaka O. Ohtsuki S. 《Solid-State Circuits, IEEE Journal of》2000,35(4):545-551
A 0.5-μm, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a temperature dependence. A variable reference voltage scheme is generated to solve this problem, boosting a fatigue-free and temperature-independent MOS reference capacitance by a driver. The driver is operated from a compact reference voltage generator that provides 32 equally divided voltages and occupies only half the layout area of a conventional one. During sense operation, memory-cell capacitance Cferr is larger than reference-cell capacitance CMOS. A double word-line pulse scheme has also been developed to eliminate a bit-line capacitance imbalance in the bit-line pairs, where a memory cell and a reference cell are separated from the bit-line pairs during sense operation. A six-order improvement in imprint lifetime has been achieved by the new scheme 相似文献
18.
《Solid-State Circuits, IEEE Journal of》1984,19(4):451-454
A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs. 相似文献
19.
This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technology nodes, and inspects both the bit-line swing (BLS) (which reflect the degradation of the cell) and the sensing delay (SD) (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the SD degradation strongly depends on the workload, supply voltage, temperature, and technology nodes (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation (up to 15.2% improvement) is more effective for the SRAM read path than cell mitigation (up to 11.4% improvement). 相似文献