A high-speed sensing scheme for 1T dynamic RAMs utilizing theclamped bit-line sense amplifier

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power     

622MHz current-mode sense amplifier

A current-mode sense amplifier, operating at 622 MHz, in a 0.8 μm CMOS process is proposed. The basic ideas are to modify the reset mechanism and precharge timing of the earlier CBLSA design to allow robust sensing with single phase clocking, as well as TSPC compatible output timing     

A novel high-speed sense amplifier for Bi-NOR flash memories

A novel high-speed current-mode sense amplifier is proposed for Bi-NOR flash memory designs. Program and erasure of the Bi-NOR technologies employ bi-directional channel FN tunneling with localized shallow P-well structures to realize the high-reliability, high-speed, and low-power operation. The proposed sensing circuit with advanced cross-coupled structure by connecting the gates of clamping transistors to the cross-coupled nodes provides excellent immunity against mismatch compared with the other sense amplifiers. Furthermore, the sensing times for various current differences and bitline capacitances and resistances are all superior to the others. The agreement between simulation and measurement indicates the sensing speed reaches 2ns for the threshold voltage difference of lower than 1 V at 1.8-V supply voltage even with the high threshold voltage of the peripheral CMOS transistors up to 0.8 V.     

A CMOS current-mode operational amplifier

A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process     

0.9 V current-mode sense amplifier using concurrent bit- and data-line tracking and sensing techniques

A novel high-speed sense amplifier for ultra-low-voltage SRAM applications is presented. It overcomes the long-unattended weaknesses of existing designs simply by forcing the data-lines to track the changes on the bit-lines. It has improved the sensing speed and the power consumption of the best prior art by 202 and 216%, respectively. Furthermore, the new design can operate down to a supply voltage of 0.9 V.     

A synthesis of a novel current-mode operational amplifier

In this letter, a novel current-mode operational amplifier (COA) is proposed. The proposed COA can operate at 2 V (±1 V) supply voltage. For high frequency operation it has only an npn transistor in signal path. Finally, SPICE simulation are shown to verify the performance of the proposed COA.     

CMOS current-mode exponential-control variable-gain amplifier

A CMOS current-mode exponential-control variable-gain amplifier is presented. It consists of a first-order current-mode pseudo-exponential circuit and a current-mode multiplier. Based on the Taylor's series expansion, the pseudo-exponential circuit can be realised by MOSFETs in saturation. The proposed circuit has been fabricated in a 0.5 μm n-well CMOS process with a gain control range of 15 dB. The experimental results confirm the feasibility of the proposed variable-gain amplifier     

High-performance current-mode instrumentation amplifier circuit

A high-performance current-mode instrumentation amplifier circuit is described in this paper. It has a high common mode rejection ratio, high gain, high accuracy, wide bandwidth and bandwidth gain-independence. It utilizes commercially available integrated circuits and is easily implemented. Experimental results show that at low frequencies a common mode rejection ratio of 120 dB is attainable.     

A match-line dynamic energy reduction technique for high-speed ternary CAM using dual feedback sense amplifier

Ternary content addressable memory (TCAM) has become popular in applications requiring high-speed table lookup. This paper presents a match-line (ML) sensing scheme to reduce dynamic energy consumption in MLs during the table lookup operation. Positive feedback has been used twice in the ML sense amplifier to achieve improved performance over existing schemes employing single feedback. Post-layout simulation of the scheme implemented using 180 nm 1.8 V CMOS logic shows that it can have match detection time as small as 907 ps. The scheme can also provide large voltage margin of 734 mV. Compared to popular current-race sensing scheme, the proposed scheme offers 83.8% energy reduction. It can achieve 64.5%, 74.7% and 77.8% energy savings compared to existing feedback schemes namely mismatch dependent, active feedback and resistive feedback, respectively. The energy saving is even larger for more advanced technology node.     

A high dynamic range current-mode amplifier for computed tomography

In this paper, we show a high dynamic range current-mode detector for computed tomography application. A regulated current mirror structure has been implemented at pixel level that provides with 17 bits dynamic range and a noise floor below 3 pARMS. Nonlinearity is kept below 2% and signal bandwidth is higher than 10 kHz. A test structure with 4/spl times/4 pixel array is presented is this paper. Both photodiode and current mode amplifier have been integrated into the same CMOS standard process.     

一种输入输出轨到轨的电流模式仪表放大器设计

本文提出了一种基于标准CMOS工艺的电流模式仪表放大器.该放大器内部运放采用斩波调制技术去除低频1/f噪声和失调,并采用正、负电荷泵,使系统具有轨到轨的输入能力.芯片使用TSMC 0.25μm CMOS混合信号工艺模型设计并流片.测试结果表明,使用60kHz的斩波频率,系统增益为40dB时,具有100dB的共模抑制比和...     

Current-mode techniques for high-speed VLSI circuits withapplication to current sense amplifier for CMOS SRAM's

The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access     

A high-speed current-multiplexed sample-and-hold amplifier with lowhold step

A monolithic high-speed sample-and-hold amplifier is described. It minimizes the hold step via a new circuit architecture. This design takes advantage of the speed of open-loop sample-and-hold circuits during the sample mode and cancellation of charge injection by duplicating and feeding it through a second amplifier during the hold mode. The unique feature of the design is an acquisition time of 150 ns to 0.01% of a 10-V step including the time required for all internal nodes to settle after the hold command is given. Aperture uncertainty is less than 20 ps and linearity is 0.003%. The device has 10-pF on-chip hold and dummy capacitors and the die size is 8.548 mm² on a junction-field-effect-transistor (JFET) plus complementary bipolar process     

A monolithic high-speed sample-and-hold amplifier for digital audio

A monolithic high-speed sample-and-hold amplifier is described which has an acquisition time of 1.5 /spl mu/s to 0.001% for a 10-V step and an aperture uncertainty of less than 0.5 ns. Distortion is 0.001% over the audio band, while in an A/D and D/A converter loop a signal-to-noise ratio better than 90 dB is measured. Chip size is 1.5/spl times/2.5 mm/SUP 2/.     

A low-power high-speed class-AB buffer amplifier forflat-panel-display application

A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 μm CMOS technology     

New current-mode wave-pipelined architectures for high-speed analog-to-digital converters

In this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-IADCs) are proposed and analyzed. In the new WP-IADC architectures, the wave-pipelined theory is applied to both pipeline structures, called full WP-IADC (FWP-IADC) and indirect transfer WP-IADC (ITWP-IADC). In the FWP-IADC, each stage uses the full current-mode wave-pipelined structure without switched-current cell circuits. In the ITWP-IADC, the switched-current cells are incorporated into the wave-pipelined stages which are divided into several sections with controlled clocks. Therefore, the proposed ITWP-IADC performs optimally in terms of speed and accuracy in the WP-IADCs. Generally, the proposed WP-IADCs have the advantages of high speed, high input frequency, high efficiency of timing usage, high clock-period flexibility in switched-current cells for precision enhancement, and reduced number of switched-current cells in the overall data path for linearity improvement. According to the theoretical analysis on the proposed WP-IADC structures, the minimum sampling clock period is proportional to the intrinsic delay of the current mirror and the increased rise/fall time in each wave-pipelined stage. The HSPICE simulation results reveal that, under Nyquist rate sampling in 8-b resolution, a sampling rate of 20 and 54 MHz can be achieved for FWP-IADC and two-section ITWP-IADC, respectively. If four wave-pipelined sections are used, the ITWP-IADC can be operated at 166 MHz at an input frequency of 8 MHz. To experimentally verify the correct function of the proposed WP-IADC structures, the proposed new architecture of the FWP-IADC is implemented by using 0.35-/spl mu/m CMOS technology. The measurement results successfully demonstrate the feasibility of wave-pipelined IADC architectures in applications of high-speed ADCs.     

一种应用于EEPROM读出放大器的设计

读出放大器是电可擦除非易失性存储器(EEPROM)中的关键模块,其读取速度决定了EEPROM的操作频率。基于国内先进的0.18μm工艺,对EEPROM放大器的基准电流源和比较器进行了分别设计,测试结果显示读出放大器的响应时间小于70 ns,可满足10 MHz的EEPROM存取速度的要求。     

Threshold difference compensated sense amplifier

A dynamic flip-flop sense amplifier compensating for threshold difference between a pair of transistors by way of offset storage technique is presented. The DC and AC analyses on input offset voltage and performance limitations are discussed. Experimental results have shown that input offset is less than 2 mV with a 5 V single power supply, over a wide temperature range and a wide common mode input voltage range.     

New high-speed monolithic operational amplifier

The limitations in the design of such amplifiers are reviewed. The stage-by-stage design of a four-stage operational amplifier with primary emphasis on speed without sacrifice of d.c. performance is presented. The layout and connection of the internal capacitor used for improvement of the frequency response are discussed. The a.c. performance and time-domain response are presented.