Electromigration under time-varying current stress

Interconnect failure as a result of electromigration is one of the major IC reliability concerns. The continuing trend of scaling-down feature sizes has exacerbated this problem. Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed DC (local V_CC and V_SS lines) and bidirectional AC (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. The goal of this review is to clarify the failure mechanisms by examining different metallization systems (Al–Si, Al–Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under pulsed DC and AC stress in a wide frequency range (from millihertz to 500 MHz). Based on these experimental results, a defect relaxation model under pulsed DC stress and a damage healing model under AC stress are developed, and electromigration design rules under these circumstances are proposed. This review shows that in the circuit operating frequency range, the “design rule current” is the time-average current for both pulsed DC and AC cases. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.     

Electromigration characteristics of tungsten plug vias under pulseand bidirectional current stressing

Using Kelvin test structures, electromigration performances of selective CVD tungsten filled vias under DC, pulsed DC, and AC current signals have been studied. The metallization consists of Al-Cu/TiW multilevel metals. The via electromigration lifetime exhibits a current polarity dependence. The via AC lifetimes are found to be much longer (more than 1000×) than DC lifetimes under the same peak stressing current density. The via lifetimes under pulsed DC stress of 50% duty factor are twice the DC lifetimes at low-frequency regions (<200 Hz) and 4-5 times the DC lifetimes at high-frequency regions (>10 kHz). The results are in agreement with the vacancy relation model     

Electromigration reliability of tungsten and aluminum vias andimprovements under AC current stress

The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region (<200 Hz) and four times the DC lifetime in the normal frequency region (> 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model     

Metal electromigration damage healing under bidirectional currentstress

The AC electromigration lifetime, without DC component, has been studied in a wide frequency range (mHz to 200 MHz) and found to be linearly proportional to the repetition frequency of the AC stressing current. This behavior is observed in both of the metallization systems (Al-2% Si and Cu) investigated. This provides further confirmation that AC lifetime is orders of magnitude longer than DC lifetime and that CMOS signal lines may be called upon to carry much larger current than allowed in present practice     

Electromigration performance of electroless platedcopper/Pd-silicide metallization

The electromigration reliability of Cu interconnects has been studied under DC, pulse-DC, and bipolar current stressing conditions. Electroless plating was used to selectively deposit Cu in oxide trenches by using Pd silicide as a catalytic layer at the bottom of the trenches to initiate copper deposition. The DC and pulse-DC lifetimes of Cu are found to be about two orders of magnitude longer than that of Al-2%Si at 275°C, and about four orders of magnitude longer than that of Al-2%Si when extrapolated to room temperature. On the other hand, Cu AC lifetimes are found to be comparable to the AC lifetimes of Al-2%Si. The pulse-DC lifetime of copper interconnects follows the similar frequency and duty factor dependence as aluminium and the prediction of the vacancy relaxation model     

Study of the impact of electromigration on integrated circuit performance and reliability at design level

Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, as it is responsible for the performance degradation. High values of temperature and current density accelerate the damage, causing an increase in the lines resistance and circuit lifetime reduction. In this work, a method is proposed to evaluate the electromigration effects in an operational amplifier circuit performance due the void growth induced by electromigration. The performance parameters are simulated by AC, DC and transient analysis for a specific temperature and time interval and the results are compared with a circuit free of electromigration. The method is used to investigate the circuit response regarding the unit gain frequency, voltage gain, cutoff frequency, output swing voltage and settling time. There are three lines that can be traditionally classified as critical due to the large current density they carry. Nevertheless, a fourth line, which has a current density below the maximum limit set by the technology being typically considered as non-critical from the layout design point of view, leads to significant reduction of the voltage gain and voltage swing, of about 59% and 14% in 5 years.     

Study of complete interconnect reliability for a GaAs MMIC power amplifier

By combining the finite element analysis (FEA) and artificial neural network (ANN) technique, the complete prediction of interconnect reliability for a monolithic microwave integrated circuit (MMIC) power amplifier (PA) at the both of direct current (DC) and alternating current (AC) operation conditions is achieved effectively in this article. As a example, a MMIC PA is modelled to study the electromigration failure of interconnect. This is the first time to study the interconnect reliability for an MMIC PA at the conditions of DC and AC operation simultaneously. By training the data from FEA, a high accuracy ANN model for PA reliability is constructed. Then, basing on the reliability database which is obtained from the ANN model, it can give important guidance for improving the reliability design for IC.     

A simulation model for electromigration in fine-line metallizationof integrated circuits due to repetitive pulsed currents

The design trend of digital very-large-scale integrated circuits (VLSI) toward higher power dissipation per chip, higher switching speeds, and smaller cross-section interconnect metallization lines has increased concern about the reliability of these devices with respect to electromigration as a failure mechanism. A simulation model for the major physical processes that influence the development and progression of electromigration damage due to pulsed electric currents is described. A comparison of model behavior to that observed experimentally for steady current (DC) stressing is made, and it is concluded that the model may provide a reasonable prediction of expected behavior under pulsed current stressing. However, experimental verification of the model is required before it can be used with assurance for design guidance     

互连铝通孔电迁移特征及其可靠性研究

研究了超大规模集成电路铝互连系统中铝通孔的电迁移失效机理及其可靠性寿命评价技术.试验采用CMOS和BiCMOS两种工艺各3组的铝通孔样品,分别在三个温度、恒定电流的加速条件下试验,以通孔开路为电迁移失效判据,最后得到了在加速条件下互连铝通孔的电迁移寿命,其结果符合标准的威布尔分布,试验准确可行.通过电迁移模型对试验数据进行了拟合,得到了激活能、电流加速因子和温度加速因子,计算出了正常工作条件下通孔电迁移的寿命,完成了对铝通孔电迁移的研究和寿命评价.     

Electromigration characteristics of copper interconnects

The electromigration characteristics of electroless plated copper interconnects have been investigated under DC and time-varying current stressing. A scheme for selected electroless Cu plating by using 150-Å Co as the seeding layer is reported. The Cu DC and pulse-DC lifetimes are found to be one and two orders of magnitude longer than that of Al-4% Cu/TiW and Al-2% Si interconnects at 275°C, and the extracted Cu lifetime at 75°C is about three and five orders of magnitude longer than that of Al-4% Cu/TiW and Al-2% Si, respectively. As previously reported for Al metallization, the Cu bipolar lifetimes were found to be orders of magnitude longer than their DC lifetimes under the same peak stressing current density because of the partial recovery of electromigration damage during the opposing phases of bipolar stressing     

Copper may destroy chip-level reliability: handle withcare-mechanism and conditions for copper migrated resistive shortformation

Although copper has a number of advantageous parameters in comparison with aluminum, and therefore, is expected to become the metallization of future high-speed, high-density silicon devices, its application introduces a new failure mechanism into the systems which has never occurred with aluminum; this is the electrochemical migration (not equal to the electromigration) resulting in short circuit formation between adjacent metallization stripes under DC bias. A great alert signal must be given for semiconductor producers in order to perform lifetime tests before introducing copper into the everyday fabrication process, otherwise the reliability of future electronic systems may dramatically be destroyed     

Experimental investigation on the impact of stress free temperature on the electromigration performance of copper dual damascene submicron interconnect

Electromigration experiments are conducted for submicron dual damascene copper lower level interconnect samples of different stress free temperatures. The electromigration life-time is found to be strongly depend on the stress state of the metallization and the stress gradient that exist due to thermal mismatch of various materials surrounding the copper metallization. It is found that by reducing the stress free temperature, electromigration lifetime can be improved. In order to explain the life-time behavior, an atomic flux divergence based coupled field finite element model is developed. The model predicts a reduction in the atomic flux divergence at the electromigration test condition due to the reduction in the stress free temperature as the key factor responsible for longer electromigration life-time observed experimentally.     

Modeling electromigration lifetime under bidirectional currentstress

Electromigration reliability of interconnect under bidirectional current stress has been studied in a wide frequency range (mHz to 200 MHz). Experimental results show that the AC lifetime rises with the stress current frequency. The current density exponent and the activation energy of AC lifetime are found to be twice that of DC lifetime. Pure AC current stress failure at extremely high current density is believed to result from thermal migration of metal at hot/cold transition points     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

Reliability of laser-induced metallic vertical links

A new method has been proposed to form electrical connections vertically between two levels of metallization by using a commercial pulsed IR laser system. Samples were stressed at accelerated current densities and temperatures. The failure activation energy has been found to be about 0.66 eV, from which electromigration is identified as a main failure mode. The extrapolated mean time to failure (MTTF) at room temperature and accelerated current density of 3 MA/cm² is about 38 years. The dependence of MTTF on laser energy has also been obtained, showing agreement with the resistance dependence on laser energy. Focused ion beam (FIB) cross sections suggest that the laser process-induced voids in the lower line limit the lifetime of links. Furthermore, a modified structure is proposed to improve the electromigration reliability. From the reliability point of view, this study shows that the laser-induced vertical link has sufficient reliability for practical implementation     

Reliability of metal interconnect after a high-current pulse

In certain situations, very large scale integration (VLSI) metal interconnects are subjected to short duration high current pulses. This occurs in FPGA programming, and in radiation testing for latchup. The authors have determined the effects of such pulsing on the long term reliability of Al (1% Cu) metallization with W cladding on top and bottom. The reliabilities of pulsed and unpulsed lines were established using accelerated electromigration testing. Lines pulsed below the immediate catastrophic threshold were seen to have slightly improved electromigration lifetimes, but as the failure threshold is approached, electromigration lifetime decreases abruptly. Therefore, high current pulsing provides no reliability hazard in this metallization system below catastrophic threshold     

交流驱动对有机电致发光器件性能的影响

OLED器件的稳定性与很多因素有关,其中驱动方式被认为是提高OLED稳定性的最重要的因素之一。我们采用优良的蓝光材料AND,并且使用NPB进行掺杂,制备了一种蓝光器件。通过对器件加反向电压处理后所表现出来的特性进行研究后,发现交流负半周期对OLED器件工作的性能的提高起着很大的作用。最后通过对同一器件分别在直流驱动和交流驱动下做寿命测试对比实验,发现在交流驱动下器件的寿命得到很大的提高。     

Experimental characterization and modelling of electromigration lifetime under unipolar pulsed current stress

The electromigration behaviour of Cu/SiCOH interconnects carrying unipolar pulsed current with long periods (i.e. 2, 16, 32 and 48 h) is presented in this study. Experimental observations suggest that the electromigration behaviour during void growth can be described by the ON-time model and that the lifetime of the Cu/SiCOH interconnects is inversely related to the duty cycle. Numerical simulation is carried out to compute the time required to nucleate a void under unipolar pulsed current stress conditions. The time to void nucleation is found to vary proportionally to the inverse square of the duty cycle and is independent of frequency at 1 Hz and higher. By computing the stress evolution in interconnects with short length, it was shown that the product of the unipolar pulsed current’s duty cycle and current density, i.e. average current density, is equivalent to the current density of a constant current (D.C.) stress. The simulation results suggest (d · jL)_crit as the equivalent critical current density-length product under unipolar pulsed current condition. Both the experimental and simulation results show that duty cycle has an effect on the electromigration lifetime of interconnects carrying unipolar pulsed current.     

Improved Stability of Pd/Ti Contacts to <Emphasis Type="Italic">p</Emphasis>-Type SiC Under Continuous DC and Pulsed DC Current Stress

The enhanced stability of Pd/Ti contacts to p-type SiC under high-current-density continuous direct-current (DC) stressing is investigated and compared with previous work on Ti/Al contacts. Additionally, differing failure modes were observed for the Pd/Ti contacts under continuous DC and pulsed DC stress. The improved stability of the Pd/Ti contacts is demonstrated through a 29% increase in the applied continuous DC current required to cause electrical failure during a 1 h test compared with the Ti/Al contacts. The metallization scheme includes a TiW barrier and a thick electroplated Au overlayer. While severe intermixing and voiding in the ohmic contact layer caused the Pd/Ti contacts to fail under continuous DC stress, electromigration of the Au overlayer degraded the contacts under pulsed DC stress. The temperature of the surface of the contacts was reduced from over 649°C for contacts that failed under continuous DC current to between 316°C and 371°C for pulsed DC current. The difference in temperature and failure modes of the continuous and pulsed DC stressed contacts indicates different failure mechanisms.     

Study of DC and AC Electromigration Behavior in Eutectic Pb-Sn Solder Joints

In this study, direct current (DC) and alternating current (AC) electromigration experiments were carried out using solder joints with a Cu/eutectic Pb-Sn/Cu joint configuration. During stressing using DC and AC, a fixed current density of 10⁴ A/cm² was applied to the joints at 150°C. In the joints stressed by DC, electromigration-induced damage occurred, and the corresponding microstructural changes mainly included valley and hillock formation in the solder region, pronounced phase segregation of Pb-rich and Sn-rich domains, asymmetric growth of Cu-Sn intermetallics at the interfaces, and excessive depletion of Cu at the cathode side. In contrast, no significant electromigration was observed after the AC treatments. This was especially true for the treatment with AC frequencies higher than 1 h⁻¹. The dependence of the damage on AC frequency suggests that electromigration in solder joints can be inhibited to a large extent when a proper reverse current is delivered.