Simultaneous double side grinding of silicon wafers: a literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of silicon wafers, covering the history, machine development (including machine configuration, drive and support systems, and control system), and process modeling (including grinding marks and wafer shape). It also discusses some possible topics for future research.     

Grinding wheels for manufacturing of silicon wafers: A literature review

Grinding is an important process for manufacturing of silicon wafers. The demand for silicon wafers with better quality and lower price presents tremendous challenges for the grinding wheels used in the silicon wafer industry. The stringent requirements for these grinding wheels include low damage on ground surfaces, self-dressing ability, consistent performance, long wheel lives, and low prices. This paper presents a literature review on grinding wheels for manufacturing of silicon wafers. It discusses recent development in abrasives, bond materials, porosity formation, and geometry design of the grinding wheels to meet the stringent requirements.     

Fine grinding of silicon wafers: a mathematical model for grinding marks

The majority of today’s integrated circuits are constructed on silicon wafers. Fine-grinding process has great potential to improve wafer quality at a low cost. Three papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third paper developed a mathematical model for the chuck shape, addressing one of the technical barriers that have hindered the widespread application of this technology: difficulty and uncertainty in chuck preparation. As a follow up, this paper addresses another technical barrier: lack of understanding on grinding marks. A mathematical model to predict the locus of the grinding lines and the distance between two adjacent grinding lines is first developed. With the developed model, the relationships between grinding marks and various process parameters (wheel rotational speed, chuck rotational speed, and wheel diameter) are then discussed. Finally, results of pilot experiments to verify the model are discussed.     

Fine grinding of silicon wafers: effects of chuck shape on grinding marks

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented the mathematical models for the chuck shape and the grinding marks, respectively. The fifth paper developed a mathematical model for the wafer shape and the sixth paper studied machine configurations for spindle angle adjustments. This paper is a follow up of the above-mentioned work. A mathematical model to predict the depth of grinding marks for any chuck shape will be first developed. With the developed model, effects of the chuck shape (as well as the wheel radius) on the depth of grinding marks will be studied. Finally, results of pilot experiments to verify the model will be discussed.     

Fine grinding of silicon wafers: machine configurations for spindle angle adjustments

This paper addresses an important aspect of silicon wafer fine grinding: machine design. For any commercially available wafer grinders, spindle angle adjustments based on the wafer shape ground is almost inevitable in order to achieve flat wafers. However, there has been no commonly accepted guidance for the design of machine configurations to ensure the easiest adjustment. Practitioners doing spindle angle adjustments have been frustrated by the difficulties of achieving the adjustments on commercial wafer grinders. This paper first illustrates such difficulties with a machine configuration frequently cited in the literature. It then demonstrates the potential ease of spindle angle adjustments with a proposed machine configuration. Next, it shows mathematically that the proposed configuration (specifically, a pair of the axes for spindle angle adjustments) is uniquely determined once the wheel diameter and wafer diameter are known. It also shows that the proposed configuration is the best in terms of ease in spindle angle adjustments. The spindle angle adjustments will be more difficult with any other configurations deviating from the proposed one.     

Fine grinding of silicon wafers: a mathematical model for the wafer shape

Over 90% of semiconductors are built on silicon wafers. The fine grinding process has great potential to produce very flat wafers at a low cost. Four papers on fine grinding have been previously published by the authors. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented mathematical models for the chuck shape and the grinding marks, respectively. As a follow up, this paper develops a mathematical model for the wafer shape. After the model is described, its practical applications in wafer manufacturing are discussed.     

An experimental investigation into soft-pad grinding of wire-sawn silicon wafers

Silicon is the primary semiconductor material used to fabricate microchips. A series of processes are required to manufacture high-quality silicon wafers. Surface grinding is one of the processes used to flatten wire-sawn wafers. A major issue in grinding of wire-sawn wafers is reduction and elimination of wire-sawing induced waviness. Results of finite element analysis have shown that soft-pad grinding is very effective in reducing the waviness. This paper presents an experimental investigation into soft-pad grinding of wire-sawn silicon wafers. Wire-sawn wafers from a same silicon ingot were used for the study to ensure that these wafers have similar waviness. These wafers were ground using two different soft pads. As a comparison, some wafers were also ground on a rigid chuck. Effectiveness of soft-pad grinding in removing waviness has been clearly demonstrated.     

A grinding-based manufacturing method for silicon wafers: generation mechanisms of central dimples on ground wafers

Silicon wafers are the fundamental building blocks for most integrated circuits. The lapping-based manufacturing method currently used to manufacture the majority of silicon wafers will not be able to meet the ever-increasing demand for flatter wafers and lower prices. A grinding-based manufacturing method has been investigated experimentally to demonstrate its potential to manufacture flat silicon wafers at a lower cost. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. This paper, as a follow up, addresses one of the reasons for the poor flatness at the wafer center: central dimples on ground wafers. A finite element model is developed to illustrate the generation mechanisms of central dimples. Then, effects of influencing factors (including Young's modulus and Poisson's ratio of the grinding wheel segment, dimensions of the wheel segment, grinding force, and chuck shape) on the central dimple sizes are studied. Pilot experimental results will be presented to substantiate the predicted results from the finite element model. This provides practical guidance to eliminate or reduce central dimples on ground wafers.     

A grinding-based manufacturing method for silicon wafers: an experimental investigation

The majority of semiconductors are built on silicon wafers. Future semiconductors will require flatter wafers with a lower price. The lapping-based manufacturing method currently used to manufacture silicon wafers will not be able to meet the ever-increasing demand cost-effectively. This paper reports an experimental investigation into a grinding-based manufacturing method, which has potential to manufacture flat silicon wafers at a lower cost. Background information on semiconductors and silicon wafers is presented first. After a discussion on drawbacks of the lapping-based method, the grinding-based method is described. Next, experimental results with the grinding-based method are presented and discussed. The results from this investigation have demonstrated the potential of the grinding-based method and revealed several directions for future work.     

Waviness removal in grinding of wire-sawn silicon wafers: 3D finite element analysis with designed experiments

Silicon wafers are used to fabricate more than 90% of integrated circuits. Surface grinding has been used to flatten wire-sawn silicon wafers. A major issue in grinding of wire-sawn wafers is that conventional grinding cannot effectively remove the waviness induced by wire-sawing process. Soft-pad grinding is a promising method to effectively remove waviness. This paper presents the results of three-dimensional (3D) finite element analysis of soft-pad grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal main effects as well as interaction effects of four factors (Young’s modulus, Poisson’s ratio, and thickness of the soft pad, and waviness wavelength of the wafer) on the effectiveness of waviness reduction. Implications of this study to manufacturing are also discussed.     

Fine grinding of silicon wafers: a mathematical model for the chuck shape

Fine grinding of silicon wafers is a patented technology to manufacture super flat semiconductor wafers cost-effectively. Two papers on fine grinding were previously published in this journal, one discussed its uniqueness and special requirements, and the other presented the results of a designed experimental investigation. As a follow up, this paper presents a study aiming at overcoming one of the technical barriers that have hindered the widespread application of this technology, namely, the difficulty and uncertainty in chuck preparation. Although the chuck shape is critically important in fine grinding, there are no standard procedures for its preparation. Furthermore, the information on the relation between the set-up parameters and the resulting chuck shape is not readily available. In this paper, a mathematical model for the chuck shape is first developed. Then the model is used to predict the relations between the chuck shape and the set-up parameters. Finally, the results of the pilot experiments to verify the model are discussed.     

Fine grinding of silicon wafers

Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of silicon wafers. In this paper, the uniqueness and the special requirements of the silicon wafer fine grinding process are introduced first. Then some experimental results on the fine grinding of silicon wafers are presented and discussed. Tests on different grinding wheels demonstrate the importance of choosing the correct wheel and an illustration of the proper selection of process parameters is included. Also discussed are the effects of the nozzle position and the flow rate of the grinding coolant.     

Fine grinding of silicon wafers: designed experiments

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure to develop cost-effective processes to manufacture silicon wafers. Fine grinding possesses great potential to reduce the overall cost for manufacturing silicon wafers. The uniqueness and the special requirements of fine grinding have been discussed in a paper published earlier in this journal. As a follow-up, this paper presents the results of a designed experimental investigation into fine grinding of silicon wafers. In this investigation, a three-variable two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feed-rate). The process outputs studied include grinding force, spindle motor current, cycle time, surface roughness and grinding marks.     

Finite element analysis for grinding of wire-sawn silicon wafers: a designed experiment

Silicon is the primary semiconductor material used to fabricate microchips. The quality of microchips depends directly on the quality of starting silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Surface grinding is one of the processes used to flatten the wire-sawn wafers. A major issue in grinding of wire-sawn wafers is the reduction and elimination of wire-sawing induced waviness. This paper presents the results of a finite element analysis for grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of four factors (wafer thickness, waviness wavelength, waviness height and grinding force) on effectiveness of waviness reduction. The implications of this study to manufacturing are also discussed.     

A study on surface grinding of 300 mm silicon wafers

Most of today's IC chips are made from 200 mm or 150 mm silicon wafers. It is estimated that the transition from 200 mm to 300 mm wafers will bring a die cost saving of 30–40%. To meet their customers' needs, silicon wafer manufacturers are actively searching for cost-effective ways to manufacture 300 mm wafers with high quality. This paper presents the results of a study on surface grinding of 300 mm silicon wafers. In this study, a three-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feedrate). The process outputs studied include spindle motor current, surface roughness, grinding marks and depth of subsurface cracks.     

ELID grinding and tribological characteristics of TiAlN film

This paper presents the results of electrolytic in-process dressing (ELID) grinding experiments performed on TiAlN film and characterization of the tribological characteristics of the produced films. In advanced films coated by physical vapor deposition, such as CrN and TiAlN, the low surface roughness required for attaining superior tribological characteristics is difficult to attain by use of only a coating process. ELID of grinding wheels improves wheel performance, enabling the attainment of specular finishes on brittle materials, with surface roughness on the nanometer scale (4 to 6 nm). In the present study, high-quality TiAlN film surfaces were fabricated by the ELID technique, typically achieving a surface roughness of around Ra 0.0024 μm by employment of a SD#30,000 wheel. Scanning electron microscopy reveals that ELID improved the finish, as indicated by the shape of grinding marks. Chemical element analysis by an energy-dispersed x-ray diffraction system suggests that ELID grinding formed an oxide layer in the machined surface of TiAlN film. Therefore, in addition to the highly smooth surface, an oxide layer formed by ELID grinding imparts superior tribological properties to ELID-ground TiAlN film.     

ELID grinding characteristics and surface modifying effects of aluminum nitride (AlN) ceramics

Aluminum nitride (AlN) ceramics have excellent electrical insulation and dielectric properties, a high thermal conductivity that is approximately 10 times that of alumina, as well as a thermal expansion coefficient that is close to that of Si, and so are anticipated to be used in semiconductor mounting boards, heat-dispersing substrates for power modules, and other heat-sink materials in a variety of high-added-value applications. In this research, ELID grinding was performed on AIN, and evaluated the processing characteristics and the resulting surface properties. The results indicate that final finishing using a #30,000 wheel produced an extremely smooth ground surface roughness of 0.008 μm Ra. In addition, the ELID series demonstrated a surface hardness and sliding characteristics superior to those of the polished series. This appears to be attributable to the diffusion phenomenon of the oxygen element produced by the ELID grinding.     

Grinding of silicon wafers using an ultrafine diamond wheel of a hybrid bond material

An ultrafine diamond wheel of a mesh size of 12,000 was fabricated by using a hybrid bond material, which consists of silicon carbide, silica and alumina. The employment of the newly developed wheel enabled excellent performance during grinding of silicon wafers. An extremely smooth surface of an average roughness of 0.6 nm was achieved. TEM examinations showed that the total thickness of the defected layer was less than 60 nm.     

电火花修形砂轮对ELID磨削效果影响的实验研究

本文对经电火花精修形、粗修形后形成硬质层和去除修形形成硬化层的金属结合剂超硬磨料砂轮进行对比实验,研究了三种砂轮的ELID电解曲线和电解后的砂轮表面形貌,分析了不同砂轮被电解后对加工工件的表面粗糙度的影响。实验结果表明：电火花修形后砂轮,表面硬质层阻值较大,不宜直接用于ELID精密镜面磨削加工;电火花修形能够提高砂轮表面的强度和硬度,能够提高砂轮的耐磨性;为保证砂轮基体受电火花淬火影响最小,形成硬质层最薄,电火花精修形时需选用较小的占空比。     

Grinding induced subsurface cracks in silicon wafers

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. To ensure high surface quality, the damage layer generated by each of the machining processes (such as lapping and grinding) has to be removed by its subsequent processes. Therefore it is essential to assess the subsurface damage for each machining process. This paper presents the observation of subsurface cracks in silicon wafers machined by surface grinding process. Based on cross-sectional microscopy methods, several crack configurations are identified. Samples taken from different locations on the wafers are examined to investigate the effects of sample location on crack depth. The effects of grinding parameters such as feedrate and wheel rotational speed on the depth of subsurface crack have been studied by a set of factorial design experiments. Furthermore, the relation between the depth of subsurface crack and the wheel grit size is experimentally determined.