A compiler infrastructure for embedded heterogeneous MPSoCs

Programming heterogeneous MPSoCs (Multi-Processor Systems on Chip) is a grand challenge for embedded SoC providers and users today. In this paper, we argue the need for and significance of positioning the language and tool design from the perspective of practicality to address this challenge. We motivate, describe and justify such a practical design of a compilation framework for heterogeneous MPSoCs targeting the domain of streaming applications, named MAPS (MPSoC Application Programming Studio). MAPS defines a clean, light-weight C language extension to capture streaming programming models. A retargetable source-to-source compiler is developed to provide key capabilities to construct practical compilation frameworks for real-world, complex MPSoC platforms. Our results have shown that MAPS is a promising compiler infrastructure that enables programming of heterogeneous MPSoCs and increases productivity of MPSoC software developers.     

Scalable communications for a million-core neural processing architecture

The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker’s hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a single 18-processor chip to over 1 million processors and to simulations of billion-neuron, trillion-synapse models, with tens of trillions of neural spike-event packets conveyed each second. The communication networks and overlying protocols are key to the successful operation of the SpiNNaker architecture, designed together to maximise performance and minimise the power demands of the platform. SpiNNaker is a work in progress, having recently reached a major milestone with the delivery of the first MPSoCs. This paper presents the architectural justification, which is now supported by preliminary measured results of silicon performance, indicating that it is indeed scalable to a million-plus processor system.     

Supporting OpenMP on a multi-cluster embedded MPSoC

The ever-increasing complexity of MPSoCs is putting the production of software on the critical path in embedded system development. Several programming models and tools have been proposed in the recent past that aim to facilitate application development for embedded MPSoCs. OpenMP is a mature and easy-to-use standard for shared memory programming, which has recently been successfully adopted in embedded MPSoC programming as well. To achieve performance, however, it is necessary that the implementation of OpenMP constructs efficiently exploits the many peculiarities of MPSoC hardware, and that custom features are provided to the programmer to control it. In this paper we consider a representative template of a modern multi-cluster embedded MPSoC and present an extensive evaluation of the cost associated with supporting OpenMP on such a machine, investigating several implementation variants that are aware of the memory hierarchy and of the heterogeneous interconnection.     

A model driven architecture for the development of smart card software

Smart cards are portable integrated devices that store and process data. Speed, security and portability properties enable smart cards to have a widespread usage in various fields including telecommunication, transportation and the credit card industry. However, the development of smart card applications is a difficult task due to hardware and software constraints. The necessity of the knowledge of both a very low-level communication protocol and a specific hardware causes smart card software development to be a big challenge for the developers. Written codes tend to be error-prone and hard to debug because of the limited memory resources. Hence, in this study, we introduce a model driven architecture which aims to facilitate smart card software development by both providing an easy design of smart card systems and automatic generation of the required smart card software from the system models. Differentiating from the previous work, the study in here contributes to the field by both providing various smart card metamodels in different abstraction layers and defines model-to-model transformations between the instances of these metamodels in order to support the realization of the same system on different smart card platforms. Applicability of the proposed methodology is shown for rapid and efficient application development in two major smart card frameworks: Java Card and ZeitControl Basic Card. Lessons learned during the industrial usage of the architecture are also reported in the paper. Finally, we discuss how the components of the architecture can be integrated in order to provide a domain-specific language for smart card software.     

LDMBL: An architecture for reducing code duplication in heavyweight binary instrumentations

Emergence of instrumentation frameworks has vastly contributed to the software engineering practices. As the instrumentation use cases become more complex, complexity of instrumenting programs also increases, leading to a higher risk of software defects, increased development time, and decreased maintainability. In security applications such as symbolic execution and taint analysis, which need to instrument a large number of instruction types, this complexity is prominent. This paper presents an architecture based on the Pin binary instrumentation framework to abstract the low‐level OS and hardware‐dependent implementation details, facilitate code reuse in heavyweight instrumentation use cases, and improve instrumenting program development time. Instructions of x86 and x86‐64 hardware architectures are formally categorized using the Z language based on the Pin framework API. This categorization is used to automate the instrumentation phase on the basis of a configuration list. Furthermore, instrumentation context data such as register data are modeled in an object‐oriented scheme. This makes it possible to focus the instrumenting program development time on writing the essential analysis logics while access to low‐level OS and hardware dependencies are streamlined. The proposed architecture is evaluated by instrumenting 135 instruction types in a concrete symbolic execution engine, resulting in a reduction of the instrumenting program size by 59.7%. Furthermore, performance overhead measure against the SPEC CINT2006 programs is limited to 8.7%.     

Specification and Standardization of a Java Trusted Computing API

The paradigm of Trusted Computing promises a new approach to improve the security of computer systems. The core functionality, based on a hardware component known as Trusted Platform Module, is integrated into commodity hardware. However, operating system integration and application software support remains limited at present. In particular, for Java, the most widely used platform‐independent computing environment, there is currently no generally accepted Trusted Computing API. In this article, we describe the design of a high‐level API for Trusted Computing. We report on the current state of the Trusted Computing Group's software architecture and on previous approaches targeting Java. We derive our requirements and design goals and describe a novel API design. We report on our transparent approach to standardization in the Java Community Process. The result of this effort is the API we propose in the Java Specification Request 321. In this work, we not only present the design of this new API but also discuss implementation and testing strategies. Copyright © 2011 John Wiley & Sons, Ltd.     

基于ARM的智能小车驱动程序的开发

介绍一种基于MiniARM的智能小车的硬件设计方案与驱动程序的开发,采用MiniARM工控板M2005-NU11为核心控制器,MiniARM内嵌μC/OS-Ⅱ操作系统,提供基本的板级驱动。本文基于该软件平台,对直流电机、温度传感器DS18B20、超声波传感器进行驱动程序开发,并将测得的数据通过串行通信传输到计算机。利用系统提供的硬件驱动支持库,无需了解硬件的细节就可通过API函数操作硬件,极大地缩短了开发时间。     

基于Struts与Hibernate框架的网络购物系统设计与实现

Struts与Hibernate是两个软件设计的框架,利用它们进行软件的开发,可以大大提高软件开发的效率。该文在深入地分析了这两种框架的基础上,把它们引入到网络购物系统的实际开发当中。并以部分模块为例详细介绍这两种框架相结合在web开发中的应用。     

An exploratory study of api changes and usages based on apache and eclipse ecosystems

Frameworks are widely used in modern software development to reduce development costs. They are accessed through their Application Programming Interfaces (APIs), which specify the contracts with client programs. When frameworks evolve, API backward-compatibility cannot always be guaranteed and client programs must upgrade to use the new releases. Because framework upgrades are not cost-free, observing API changes and usages together at fine-grained levels is necessary to help developers understand, assess, and forecast the cost of each framework upgrade. Whereas previous work studied API changes in frameworks and API usages in client programs separately, we analyse and classify API changes and usages together in 22 framework releases from the Apache and Eclipse ecosystems and their client programs. We find that (1) missing classes and methods happen more often in frameworks and affect client programs more often than the other API change types do, (2) missing interfaces occur rarely in frameworks but affect client programs often, (3) framework APIs are used on average in 35 % of client classes and interfaces, (4) most of such usages could be encapsulated locally and reduced in number, and (5) about 11 % of APIs usages could cause ripple effects in client programs when these APIs change. Based on these findings, we provide suggestions for developers and researchers to reduce the impact of API evolution through language mechanisms and design strategies.     

Design and implementation of an operating system for composable processor sharing

Multi-Processor Systems on Chip (MPSoC) run multiple independent applications, often developed by different parties. The applications share the hardware resources, e.g. processors, memories and interconnect. The sharing typically causes interference between the applications, which severely complicates system integration and verification. Even if the applications are verified in isolation, the system designer must verify the combined behaviour, leading to an explosion in design complexity. Composable MPSoCs have no interference between applications, thus allowing independent design and verification. For an MPSoC to be composable, all the hardware resources must offer composability. A particularly challenging resource is the processors, often purchased as off-the-shelf intellectual property.In this work we present the design and implementation of CompOSe, a light-weight (only 1500 lines of code) composable operating system for MPSoCs. CompOSe uses fixed-size time slices, coupled with a composable scheduler, to enable composable processor sharing. Using instances of ARM7, ARM11 and the Xilinx MicroBlaze we experimentally demonstrate the ability to provide temporal composability, even in the presence of dynamic application behaviour and multiple use cases. We do so using a diverse set of processor architectures, without requiring any hardware modifications. We also show how CompOSe allows slack to be distributed within and between applications through a novel two-level scheduler and slack-distribution system.     

J2EE Web开发框架体系结构

开源框架（如MVC框架Struts、OR Mapping框架Hibernate、Log框架Log4j等）的出现极大地提高了J2EE应用程序开发的效率,但它们都只提供了应用程序某一层次的框架,不是一个完整的应用框架。应用框架是整个系统的可重用设计,是构建应用程序的模板,它本质上是一系列设计模式的抽象实现,并提供一些框架基础服务。在整合各种框架的基础上,我们在一个更高的层面上设计和实现了一个J2EEWeb开发框架。该开发框架具有良好的软件体系结构,采用了多种架构设计模式（如多层结构、MVC模式、IoC模式等）,保证了程序具有松耦合性和易扩展性,并提供了一些常用的可复用构件,实现了web应用系统的基础功能。它可以帮助开发人员获得最大程度的框架复用,快速开发应用系统。     

Customizing system software using OO frameworks

Today's applications have exploded in their diversity, but most operating systems are still general-purpose and inefficient. One of the benefits of using an OO approach is the ability to modify very small details of an operating system, which makes it easy to tailor the system to the application. My experience indicates that optimizing an operating system for the general case can result in mediocre performance for specialized applications, especially parallel applications. Therefore, I envision a customizable operating system built from components that will allow an optimal match between application behavior and hardware architecture. I propose an object-oriented operating system in which design frameworks support alternative implementations of key systems software services     

仿生硬件在线进化技术研究

仿生硬件是一门新兴的研究领域,它提供了一种基于进化的电路设计新方法.目前,国内的研究主要以离线进化为主.介绍了仿生硬件的在线进化,给出了电路进化系统的硬件结构和软件流程.实例证明基于进化算法、JBits API和RC1000板卡实现硬件在线进化是可行的.     

Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems

Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for mobile and ubiquitous systems. In this work, we present the internal architecture and design flow of a newly proposed framework called Verifiable Embedded Real-Time Application Framework (VERTAF), which integrates three techniques namely software component-based reuse, formal synthesis, and formal verification. Component reuse is based on a formal unified modeling language (UML) real-time embedded object model. Formal synthesis employs quasi-static and quasi-dynamic scheduling with multi-layer portable efficient code generation, which can output either real-time operating systems (RTOS)-specific application code or automatically generated real-time executive with application code. Formal verification integrates a model checker kernel from state graph manipulators (SGM), by adapting it for embedded software. The proposed architecture for VERTAF is component-based which allows plug-and-play for the scheduler and the verifier. The architecture is also easily extensible because reusable hardware and software design components can be added. Application examples developed using VERTAF demonstrate significantly reduced relative design effort as compared to design without VERTAF, which also shows how high-level reuse of software components combined with automatic synthesis and verification increases design productivity.     

基于Delphi的GetSystemMetrics函数应用

GetSystemMetrics函数是Windows API(Application Program Interface)函数中的一员。利用这一函数,可以获取很多关于系统的信息,包括软件系统和硬件系统等,对于面向计算机软、硬件系统检测、维护的应用程序开发有重要的应用价值。本文讨论了Delphi下GetSystemMetrics函数的典型应用,并提供对应的程序验证。     

Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits

The design of system-on-a-chip (SoC) circuits requires the integration of complex hardware/software components that are customized to efficiently execute a specific application. Nowadays, these components include many different embedded processors executing concurrent software tasks. In this paper, we present an object-based component interconnection model to represent both hardware and software components within a system architecture in a very high level of abstraction. This model is used in a design flow for automatic generation of hardware/software interfaces for SoC circuits. Design tools for automatic generation of embedded operating systems, hardware interfaces and associated device drivers are presented and evaluated using the results obtained with a VDSL application.     

Computing reliability: On the differences between software testing and software fault injection techniques

System reliability has become a main concern during the computer-based system design process. It is one of the most important characteristics of the system quality. The continuous increase of the system complexity makes the reliability evaluation extremely costly. Therefore, there is need to develop new methods with less cost and effort. Furthermore, the system is vulnerable to both software and hardware faults. While the software faults are usually introduced by the programmer either at the design or the implementation stage of the software, the hardware faults are caused by physical phenomena affecting the hardware components, such as environmental perturbations, manufacturing defects, and aging-related phenomena. The software faults can only impact the software components. However, the hardware faults can propagate through the different system layers, and affect both the hardware and the software. This paper discusses the differences between the software testing and the software fault injections techniques used for reliability evaluation. We describe the mutation analysis as a method mainly used in software testing. Then, we detail the fault injection as a technique to evaluate the system reliability. Finally, we discuss how to use software mutation analysis in order to evaluate, at software level, the system reliability against hardware faults. The main advantage of this technique is its usability at early design stage of the system, when the instruction set architecture is not available. Experimental results run to evaluate faults occurring the memory show that the proposed approach significantly reduces the complexity of the system reliability evaluation in terms of time and cost.     

A functional framework for Web-based information visualizationsystems

The accelerating evolution of information visualization research in the last few years has led to several specific system implementations. The obvious drawbacks of this development are highly dependent software systems, which are only available for a restricted number of users. Today, due to the remarkable advances in hardware and software technologies, not only very expensive graphics workstations, but also low-cost PCs are capable of running computational demanding visualization systems. Furthermore, the rapid development of the medium World Wide Web along with state-of-the-art Internet programming techniques has led to a trend toward more generally usable visualization systems. In this paper, we propose a functional developer's framework for general Web-based visualization systems which makes intelligent use of application specific software and hardware components on the server side, as well as Java's benefits on the client side. To demonstrate the framework's abilities, we have applied it to two practical visualization tasks and report on our experience concerning practicability and pitfalls     

面向工程的SoC技术及其挑战

系统集成芯片(SoC)是21世纪集成电路的发展方向，它以IP核复用技术、超深亚微米工艺技术和软硬件协同设计技术为支撑，是系统集成和微电子设计领域的一场革命。该文阐述了SoC的设计与验证、IP的开发与复用以及工程化SoC所面临的超深亚微米下的物理综合、软硬件协同设计、低功耗设计、可测性设计和可重用技术等方面的挑战。     

Codesign of embedded systems: status and trends

Ever increasing embedded system design complexity combined with a very tight time-to-market window has revolutionized the embedded-system design process. The concurrent design of hardware and software has displaced traditional sequential design. Further, hardware and software design now begins before the system architecture (or even the specification) is finalised. System architects, customers, and marketing departments develop requirement definitions and system specifications together. System architects define a system architecture consisting of cooperating system functions that form the basis of concurrent hardware and software design. Interface design requires the participation of both hardware and software developers. The next step integrates and tests hardware and software-this phase consists of many individual steps. Reusing components taken from previous designs or acquired from outside the design group is a main design goal to improve productivity and reduce design risk. It is argued that new methodologies and AD tools support an integrated hardware software codesign process