Contact Resistance in Nanocrystalline Silicon Thin-Film Transistors

Thin-film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) made by plasma-enhanced chemical vapor deposition have higher electron and hole field-effect mobilities than their amorphous counterparts. However, as the intrinsic carrier mobilities are raised, the effective carrier mobilities easily can become limited by the source/drain contact resistance. To evaluate the contact resistance, the nc-Si:H TFTs are made with a range of channel lengths. The TFTs are fabricated in a staggered top-gate bottom source/drain geometry. Both the intrinsic and the - or -doped nc-Si:H source/drain layers are deposited at 80-MHz excitation frequency at a substrate temperature of 150 . Transmission electron microscopy of the TFT cross section indicates that crystallites of doped nc-Si:H nucleate on top of the Cr source/drain contacts. As the film thickness increases, the crystallites coalesce, and the leaf-shaped crystal grains extend through the doped layer to the channel i layer. The contact resistance is estimated by measuring I_DS for several channel lengths at fixed gate and drain voltages. The results show that the contact resistance depends on the gate voltage and that the source/drain current of these TFTs at V_{DS =} 10 V becomes limited by the contact resistance when the channel length is less than 10 mum for n-channel and less than 25 mum for p-channel.     

Numerical Simulation of Low-Frequency Noise in Polysilicon Thin-Film Transistors

Numerical simulations of low-frequency noise are carried out in two technologies of N-channel polysilicon thin-film transistors (TFTs) biased from weak to strong inversion and operating in the linear mode. Noise is simulated by generation/recombination processes. The contribution of grain boundaries on the noise level is higher in the strong inversion region. The microscopic noise parameter that is deduced from numerical simulations is lower than the macroscopic one defined according to the Hooge empirical relationship and deduced from noise measurements. The higher macroscopic value is attributed to the drain-current crowding induced by nonconducting spots in the devices due to structural defects. The ratio of these two noise parameters can be considered as an indicator to qualify TFT technology.     

非晶硅薄膜晶体管的泄漏电流模型

当对a-Si:H TFT施加较大的漏-栅电压时,其泄漏电流主要取决于空穴在漏端耗尽区内的产生过程以及被有源层内中立陷阱捕获的过程.基于价带空穴和被陷阱所捕获空穴的一维连续性方程,推导出空穴在有源层内纵向传导的逃逸率.通过描述漏端耗尽区内空穴的产生率以及在a-Sic H层内空穴传导的逃逸率,建立了a-Si:H TFT的泄漏电流模型,并进行了相应验证.     

Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.     

Reduction of Leakage and Low-Frequency Noise in MOS Transistors Through Two-Step RTA of NiSi-Silicide Technology

A two-step rapid thermal annealing (RTA) nickel salicidation process was employed to fabricate 0.1-$muhboxm$gate length CMOS transistors. Excess salicidation, common in the conventional one-step RTA NiSi process, is effectively suppressed by this approach, which is confirmed by transmission electron microscopy (TEM) images. More improvements due to two-step NiSi are observed in NMOS than in PMOS transistors: The$ n^+- p$junction diode with two-step NiSi exhibits lower reverse leakage and higher breakdown voltage than the one-step silicided diode. For the first time, it is found that two-step NiSi NMOS exhibits significant reduction in off-state leakage$(sim!hbox5times)$and low-frequency noise (up to two orders of magnitude) over one-step NiSi NMOS, although there is not much difference in PMOS transistors.     

多晶硅薄膜晶体管泄漏电流建模研究与进展

泄漏电流是多晶硅薄膜晶体管应用的一个主要问题.多晶硅薄膜晶体管泄漏电流的建模对集成多晶硅薄膜晶体管设计和工艺改进具有重要意义.总结了多晶硅薄膜晶体管泄漏电流建模思想,并对三种基于不同物理机制的典型模型进行了评述,分析讨论了其优缺点;最后,对当前建模工作进行了总结与展望.     

Improving Switching Performance of Thin-Film Transistors in Disordered Silicon

The silicon integrated electronics on glass or plastic substrates attracts wide interests. The design, however, depends critically on the switching performance of transistors, which is limited by the quality of silicon films due to the materials and substrate process constraints. Here, the ultrathin channel device structure is proposed to address this problem. In a previous work, the ultrathin channel transistor was demonstrated as an excellent candidate for ultralow power memory design. In this letter, theoretical analysis shows that, for an ultrathin channel transistor, as the channel becomes thinner, stronger quantum confinement can induce a marked reduction of OFF-state leakage current (I_OFF), and the subthreshold swing (S) is also decreased due to stronger control of channel from the gate. Experimental results based on the fabricated nanocrystalline silicon thin-film transistors prove the theoretical analysis. For the 2.0-nm-thick channel devices, I_ON/I_OFF ratio of more than 10¹¹ can be achieved, which can never be obtained for normal thick channel transistors in disordered silicon.     

Low-Frequency Noise Partition of Asymmetric MOS Transistors Operating in Linear Regime

The low-frequency noise in asymmetric MOS transistors with graded channel doping from the source to the drain can be partitioned by assuming a series connection of two or more transistors along the device's channel length. The partition explains the noise overshoot at gate biases around the threshold voltage of the composite device. Expressions for the input-referred gate noise voltage are obtained and verified.      

Analysis of Negative Bias Temperature Instability in Body-Tied Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.     

低温硅双极晶体管电流增益研究

着重分析了多晶硅发射极对提高电流增益的作用和低温下集电区中性杂质碰撞电离引起的电流倍增效应，导出多晶硅发射极晶体管电流增益的表达式，很好地解释了实验结果。     

Crystallization of Double-Layered Silicon Thin Films by Solid Green Laser Annealing for High-Performance Thin-Film Transistors

We report a new laser crystallization method employing double-layered amorphous-Si ( $a$-Si) thin films for solid green laser annealing (GLA) crystallization that is called GLA double-layered x'tallization (GLADLAX). Crystallization of the upper and lower $a$-Si layers of the double-layered substrate at a single laser scanning was achieved, with the upper $a$-Si becoming poly-Si with very large crystal grains and the lower $a$-Si layer becoming microcrystalline Si. Thin-film transistors using the upper layer of poly-Si that is crystallized by the method as their active channels had excellent switching performance, with their mobility exceeding 350 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$, demonstrating promising applicability of GLADLAX to thin-film electronics.      

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10⁷ to 1.39 times 10⁷. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.     

Gallium–Indium–Zinc-Oxide-Based Thin-Film Transistors: Influence of the Source/Drain Material

During the last years, oxide semiconductors have shown that they will have a key role in the future of electronics. In fact, several research groups have already presented working devices with remarkable electrical and optical properties based on these materials, mainly thin-film transistors (TFTs). Most of these TFTs use indium-tin oxide (ITO) as the material for source/drain electrodes. This paper focuses on the investigation of different materials to replace ITO in inverted-staggered TFTs based on gallium-indium-zinc oxide (GIZO) semiconductor. The analyzed electrode materials were indium-zinc oxide, Ti, Al, Mo, and Ti/Au, with each of these materials used in two different kinds of devices: one was annealed after GIZO channel deposition but prior to source/drain deposition, and the other was annealed at the end of device production. The results show an improvement on the electrical properties when the annealing is performed at the end (for instance, with Ti/Au electrodes, mobility rises from 19 to 25 cm²/V ldr s, and turn-on voltage drops from 4 to 2 V). Using time-of-flight secondary ion mass spectrometry (TOF-SIMS), we could confirm that some diffusion exists in the source/drain electrodes/semiconductor interface, which is in close agreement with the obtained electrical properties. In addition to TOF-SIMS results for relevant elements, electrical characterization is presented for each kind of device, including the extraction of source/drain series resistances and TFT intrinsic parameters, such as (intrinsic mobility) and VT_i (intrinsic threshold voltage).     

硅双极晶体管1／f噪声的物理机制

在低频下,1/f噪声是硅双极晶体管的主要噪声。到目前为止,一般认为,1/f噪声有二种来源:表面态的存在和体内自由载流子迁移率的涨落。这两种1/f噪声有不同的表现形式。目前还没有统一的模型来描述1/f噪声,这是由于对1/f噪声的物理机理还没有一个完整、统一的理论。本文对已见发表的1/f噪声主要研究结果作了评述。     

Photocurrent Study of Oxygen-Mediated Doping States in Pentacene Thin-Film Transistors

We have measured and analyzed the gate-bias dependence of the photocurrent in pentacene organic field-effect transistors which have been doped using a UV–ozone treatment and compared these to the response of identical devices produced with no air or ozone exposure. The wavelength-dependent photocurrent spectrum shows intensified photocurrent peaks in oxygen-doped samples in the range of 350–480 nm, which corresponds to energy transitions (2.66, 2.76, 2.95, and 3.15 eV) larger than the pentacene HOMO–LUMO gap. These peaks are attributed to the formation of excitons and improved dissociation into electrons and holes, owing to the trap states formed at the interface between the UV-treated dielectric and the pentacene, which also account for positively shifted threshold voltage in the UV-treated sample. Our results are consistent with the trap-and-release transport model for pentacene. The gate-bias-dependent photocurrent spectrum shows that the photocurrent intensity is proportional to the mobility in the linear region, and this mobility relationship was confirmed via simultaneous transport measurement in the device.      

Microwave Noise Characterization of GaAs MESFET's: Evaluation by On-Wafer Low-Frequency Output Noise Current Measurement

A simplified noise equivalent circuit is presented for submicron-gate-length MESFET's in the common-source configuration, consisting of five linear circuit elements: the gate-to source capacitance C/sub gs/, the total input resistance R/sub T/, the transconductance g/sub m/, the output resistance R/sub 0/, and a noise current source of spectral density S/sub io/ at the output port. All of these elements can be determined by on-wafer measurements, and the noise current can be measured at a low frequency. The minimum noise figure of the device calculated from this model, as well as the bias and frequency dependence of the noise figure, is shown to be in agreement with microwave noise figure measurements. Thus a technique has been established for determination of the minimum noise figure of a device solely by on-wafer measurements rather than by the usual microwave measurements. The proposed technique can be employed rapidly, conveniently, without the need for tuning, and at the wafer stage of device fabrication.     

基于溶液法的金属诱导碟型晶畴多晶硅薄膜和薄膜晶体管的研究

以非晶硅为晶化前驱物,采用镍盐溶液浸沾的方法可以得到超大尺寸碟型晶畴结构的低温多晶硅薄膜.所得多晶硅薄膜的平均晶畴尺寸大约为50 μm,空穴的最高霍尔迁移率为30.8 cm~2/V·s,电子的最高霍尔迁移率为45.6 cm~2/V·s.用这种多晶硅薄膜为有源层,所得多晶硅TFT的场效应迁移率典型值为70～80 cm~2 /V·s,亚阈值斜摆幅为1.5 V/decade,开关电流比为1.01×10~7,开启电压为-8.3 V.另外,P型的TFT在高栅偏压和热载流子偏压下具有良好的器件稳定性.     

多晶硅薄膜晶体管泄漏电流建模

泄漏电流是多晶硅薄膜晶体管应用的一个主要问题,多晶硅薄膜晶体管泄漏电流的建模对集成多晶硅薄膜晶体管设计和工艺改进具有重要意义.本文以陷阱辅助热电子场致发射理论为基础,通过对物理模型的近似处理,提出了一个在大的栅压范围和温度范围内与实验数据吻合较好的多晶硅薄膜晶体管泄漏电流解析模型.模型适合于电路仿真器.     

On the Low-Frequency Noise of pMOSFETs With Embedded SiGe Source/Drain and Fully Silicided Metal Gate

The low-frequency noise of silicon pMOSFETs with embedded SiGe source/drain (S/D) regions is studied. The gate stack consists of HfSiON/SiO₂ covered by a fully silicided gate electrode. S/D regions with different Ge content and thickness have been processed. It is shown that, while mobility and drive current are significantly enhanced by this strain-engineering approach, the 1/f noise is little affected, irrespective of the germanium content or thickness of the epitaxial SiGe S/D layers, i.e., the amount of compressive strain in the channel. From this, it is derived that, first of all, the embedded (S/D) processing does not degrade the gate-stack quality and that, second, no evidence of an intrinsic strain effect on the 1/f noise is observed here.     

Conduction Mechanisms and Low-Frequency Electrical Noise Studies in pin InGaAs/InAlAs Strained MQW Photodiodes

The current–voltage (I–V) characteristics as a function of temperature of different strained multiple-quantum-well pin InGaAs/InAlAs photodiodes were investigated in the dark from 15 K to 300 K. Analysis of the slope variation of the I–V curves as a function of temperature, under forward bias, indicate a conduction mechanism by tunneling effect assisted by recombination centers. For temperatures below around 100 K, as the voltage increases, a negative resistance appears, followed by oscillations suggesting a sequential resonant tunneling between electronic states of the quantum wells. Low frequency electrical noise measurements performed at 300 K between 1 and$10^5$Hz confirm the existence of recombination centers.