Computationally efficient methods for blind decision feedback equalization of QAM signals

This paper investigates computationally efficient methods for blind decision feedback equalization (DFE) that reduce the complexity and power requirements of blind equalization algorithms while maintaining their steady-state characteristics for quadrature amplitude modulation (QAM) signals. These include the power-of-two error (POT), selective coefficient update (SCU), and frequency-domain block (FDB) methods. A novel radius-directed stop-and-go (RSG) method is introduced, which selectively adjusts the equalizer tap coefficients based on the equalizer output radius. In addition, a new activation/de-activation method based on the equalizer output radius is utilized to control the feedback equalizer (FBE) of the DFEs. Simulation studies and analysis are provided for empirically derived cable and microwave channels and Ricean fading channels.     

An efficient decision feedback equalizer for the ATSC DTV receiver

In this paper an efficient decision feedback equalizer is presented for the equalization of the received signal in the eight level vestigial sideband, Advanced Television Systems Committee, digital television system, adopting a novel detection rule for symbol detection at the output of the equalizer. The conventional hard limiter is replaced by an efficient symbol detection algorithm, based on the underlying trellis coded modulated coding of the transmitted symbols. The proposed decision device has a marginal computational cost and it can be implemented using simple combinatorial and sequential logic circuitry. When the equalizer operates in the decision directed mode, the normalized least mean squared algorithm is utilized for the adaptation of the equalizer coefficients, in a “stop-and-go” like mode, triggered by a reliability signal associated to the detected symbols. The performance of the proposed method is illustrated by typical computer simulation.     

Adaptive multichannel decision feedback equalization for volterra type nonlinear communication channels

A model-based approach for the decision feedback equalization of Volterra type nonlinear communication channels is proposed such that the linear model-based decision feedback equalization can be considered as a special case of the proposed approach. In designing the decision feedback equalizer, the nonlinear decision feedback equalization problem is visualized as a linear, multichannel equalization problem. A complete modified Gram–Schmidt orthogonalization of the input vector is achieved by using modified sequential processing multichannel lattice stages. The elements of the multichannel desired signal vector are then estimated from the new orthogonal set by using only scalar operations. The probability of error performance of the proposed equalizer is improved by the estimation of the elements of the desired signal vector through a sigmoid activation function so that a polynomial perceptron equalizer is realized. The comparative computational complexity calculations and performance results of the proposed decision feedback equalizer are also provided.     

非线性信道判决反馈均衡器

本文针对严重线性失真、轻度非线性失真的信道提出了一种简单实用的非线性信道判决反馈均衡器。它是一个将关联模型非线性信道均衡器与线性信道判决反馈均衡器相结合的产物。对典型的非线性信道模型所做的模拟试验表明,该均衡器不仅简单实用、便于实时处理,而且均衡性能得到较大的改善。     

A NEW ADAPTIVE EQUALIZER STRUCTURE FOR NONLINEAR CHANNELS

Based on the analysis of nonlinear channel models,a new connectionist model ofadaptive equalizer is constructed.Comparing with the connectionist model using the Volterraseries to extend the input vector space,the number of weights with the new structure is reducedsignificantly.It is shown by simulations that the weight values of the new scheme converge to theoptimal values closely for non-minimum phase channels as well minimum phase channels,if thechannel noise is small enough.Testing results of the BER(Bit Error Rate)tell us that the newadaptive equalizer for nonlinear channels is superior to the conventional linear equalizers in theequalization performances.     

Frequency domain decision feedback equalizer for time-reversal space-time block coding

In this paper,a frequency domain decision feedback equalizer is proposed for single carrier transmission with time-reversal space-time block coding (TR-STBC).It is shown that the diagonal decision feed...     

Adaptive Bayesian decision feedback equalizer for dispersive mobileradio channels

The paper investigates adaptive equalization of time-dispersive mobile radio fading channels and develops a robust high performance Bayesian decision feedback equalizer (DFE). The characteristics and implementation aspects of this Bayesian DFE are analyzed, and its performance is compared with those of the conventional symbol or fractional spaced DFE and the maximum likelihood sequence estimator (MLSE). In terms of computational complexity, the adaptive Bayesian DFE is slightly more complex than the conventional DFE but is much simpler than the adaptive MLSE. In terms of error rate in symbol detection, the adaptive Bayesian DFE outperforms the conventional DFE dramatically. Moreover, for severely fading multipath channels, the adaptive MLSE exhibits significant degradation from the theoretical optimal performance and becomes inferior to the adaptive Bayesian DFE     

Adaptive quantization for fading channels with feedback

The effect of the presence of a feedback channel on the transmission of information was first considered by Shannon, who showed that the capacity of a memoryless channel is not increased by the existence of a feedback link even if the feedback link is noiseless. Later it was shown that the information on a feedback channel can be used to improve considerably the performance of channel coding. In this work we study the transmission of an information source through a fading channel with feedback, modeled by a finite-state channel in the Gilbert-Elliot sense. We show that by employing the feedback information in the quantizer design for this finite-state channel, one can achieve lower overall distortion compared to the case where feedback is not available. The feedback channel is used to estimate the channel state using a hidden Markov model, and a quantizer matched to the channel state is chosen based on this information.     

基于非单点模糊RBF网络的判决反馈均衡器

提出了一种具有较强抗突发干扰能力的非单点模糊径向基函数（Radial Basis Function,RBF）网络判决反馈均衡器.该方法将具有前置滤波特性的非单点模糊化技术引入RBF网络,利用梯度下降法自适应调整参数.通过仿真实验,并与基于径向基函数网络的判决反馈均衡器（Radial Basis Function Network-Decision Feedback Equalizer,RBFN-DFE）和传统判决反馈均衡器（Decision Feedback Equalizer,DFE）进行比较,结果证明该方法抗突发干扰能力强,误码性能好.     

双判决反馈均衡的改进算法研究

本文提出了双判决反馈均衡器（DDFE）的一种改进结构－双DDFE（Dual DDFE)。模拟研究表明,双DDFE性能要比DDFE提高0．5dB-1dB,而其实现复杂性相对于DDFE增加不大。     

Spatial and temporal adaptive receiver for DS-CDMA systems

The objective of this paper is to propose a reception scheme to improve the performance of DS-CDMA (Direct Sequence Code Division Multiple Access) systems, compared to conventional direct channel receivers. The technique employs a spatial and temporal adaptive receiver composed of N spatial processors (associated with M antennas) and N Decision Feedback Equalizers (DFE), both of which are trained using a TMDP (Time Multiplexed Dedicated Pilot) sequence. The spatial and temporal receiver associated with TMDP offers considerable benefits when compared to the conventional Rake-Finger receiver. Performance results and details of the functioning of the proposed reception scheme are presented.     

A decision feedback equalizer with time-reversal structure

This work describes the use of a receiver with a time-reversal structure for low-complexity decision feedback equalization of slowly fading dispersive indoor radio channels. Time-reversal is done by storing each block of received signal samples in a buffer and reversing the sequential order of the signal samples in time prior to equalization. As a result, the equivalent channel impulse response as seen by the equalizer is a time-reverse of the actual channel impulse response. Selective time-reversal operation, therefore, allows a decision feedback equalizer (DFE) with a small number of forward filter taps to perform equally well for both minimum-phase and maximum-phase channel characteristics. The author evaluates the theoretical performance bounds for such a receiver and quantifies the possible performance improvement for discrete multipath channels with Rayleigh fading statistics. Two extreme cases of DFE examples are considered: an infinite-length DFE; and a DFE with a single forward filter tap. Optimum burst and symbol timing recovery is addressed and several practical schemes are suggested. Simulation results are presented. The combined use of equalization and diversity reception is considered     

A fast computation algorithm for the decision feedback equalizer

A novel fast algorithm for computing the minimum MSE decision feedback equalizer settings is proposed. The equalizer filters are computed indirectly, first by estimating the channel, and then by computing the coefficients in the frequency domain with the discrete Fourier transform (DFT). Approximating the correlation matrices by circulant matrices facilitates the whole computation with very small performance loss. The fractionally spaced equalizer settings are derived. The performance of the fast algorithm is evaluated through simulation. The effects of the channel estimation error and finite precision arithmetic are briefly analyzed. Results of simulation show the superiority of the proposed scheme     

无人机数据链判决反馈均衡器的FPGA实现

从无人机数据链的需求出发,使用现场可编程门阵列(FPGA)实现判决反馈均衡器(DFE),以消除无人机数据链中的码间干扰。文中利用System Generator对判决反馈均衡器进行建模,将模型转换为硬件,并通过硬件协调仿真在Xilinx virtex5 XC5VSX50T芯片上验证。仿真结果表明,在不同信道条件下,判决反馈均衡器能很好地克服码间干扰,适用于无人机信道。本文为无人机高速数据链均衡器的实现打下基础。     

A study of analog decision feedback equalization for ADC-Based serial link receivers

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better programmability with different channel characteristics and the possibility of employing powerful signal equalization techniques in the digital domain. However, complexity and power consumption are still major issues in adopting such receivers in high-speed applications when compared to traditional binary or mixed-signal approaches. Embedded decision feedback equalization (DFE) before ADC quantization can relax the design requirements of both the ADC and post-ADC digital processing. This paper studies the impact of embedded analog DFE on voltage margin improvement of an ADC-based receiver through worst-case analysis. An analytical expression for the link bit-error-rate (BER) with analog DFE is derived and validated through simulations. An empirical study is conducted that evaluates the achievable BER of embedded analog DFE as a function of the channel inter-symbol interference (ISI) and ADC resolution. A channel-dependent parameter is introduced and employed to quantify the BER improvement achieved by embedding analog DFE in a receiver. A prototype receiver with embedded DFE is designed and laid out in a 130 nm CMOS process and achieves 4.64-bits peak ENOB and 4.08 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. The BER performance of the receiver over high-loss FR4 channels at 1.6 Gb/s is evaluated and used to validate the simulation results.     

A blind decision feedback equalizer incorporating fixed lagsmoothing

A new type of blind decision feedback equalizer (DFE) incorporating fixed lag smoothing is developed in this paper. The structure is motivated by the fact that if we make full use of the dependence of the observed data on a given transmitted symbol, delayed decisions may produce better estimates of that symbol. To this end, we use a hidden Markov model (HMM) suboptimal formulation that offers a good tradeoff between computational complexity and bit error rate (BER) performance. The proposed equalizer also provides estimates of the channel coefficients and operates adaptively (so that it can adapt to a fading channel for instance) by means of an online version of the expectation-maximization (EM) algorithm. The resulting equalizer structure takes the form of a linear feedback system including a quantizer, and hence, it is easily implemented. In fact, because of its feedback structure, the proposed equalizer shows some similarities with the well-known DFE. A full theoretical analysis of the initial version of the algorithm is not available, but a characterization of a simplified version is provided. We demonstrate that compared to the zero-forcing DFE (ZF-DFE), the algorithm yields many improvements. A large range of simulations on finite impulse response (FIR) channels and on typical fading GSM channel models illustrate the potential of the proposed equalizer     

A decision-feedback equalizer with pattern-dependent feedback formagnetic recording channels

A new nonlinear equalizer for high-density magnetic recording channels is presented. It has a structure of the decision-feedback equalizer (DFE) with a nonlinear model at the feedback section and a dynamic threshold detector. The feedback nonlinear model is a sequence of look-up tables (LUTs) indexed by time, and each table is addressed by a transition pattern formed by one future and ν past transitions. We call this new nonlinear equalizer the pattern-dependent DFE (PDFE). The feedback nonlinear model cancels the trailing nonlinear intersymbol interference (ISI), and then the data decision is made by considering the precursor nonlinear ISI caused by one future symbol. We propose a tap optimization criterion SNR_d for the PDFE which in effect tries to maximize the output signal to noise ratio, and derive a closed-form solution for the tap values. We compare the detection performance of PDFE with that of the DFE and the RAM-DFE on experimental channels. The RAM-DFE is a DFE with one large LUT at its feedback section. The results show that the PDFE yields a significant performance improvement over the DFE and the RAM-DFE. Also the PDFE derived in this paper achieves a superior performance compared with the PDFE derived by the minimum mean-square-error criterion     

基于噪声预测的低复杂度判决反馈均衡

针对散射通信系统多径效应严重，常用的频域非线性均衡算法复杂度过高的情况，提出了一种基于噪声预测的低复杂度判决反馈均衡方法。根据常用散射通信多径信道模型，在时延功率谱呈指数衰减的情况下，通过曲线拟合的方法预测非线性判决反馈均衡器的部分系数，从而达到降低算法复杂度的目的。仿真结果表明，所提方法不仅具有较低的复杂度，也具备良好的误码性能，在合适的阈值下，与原有算法的性能损失可控制在0.1 dB以内。     

An LMS-based decision feedback equalizer for IS-136 receivers

In digital mobile communication systems, intersymbol interference is one of the main causes of degrading system performance. Decision feedback equalization (DFE) is the commonly used remedy for this problem. Since the channel is fast-varying, an adaptive algorithm possessing a fast convergence property is then required. The least mean square (LMS) algorithm is well known for its simplicity and robustness; however, its convergence is slow. As a consequence, the LMS algorithm is rarely considered in this application. In this paper, we consider an LMS-based DFE for the North American IS-136 system. We propose an extended multiple-training LMS algorithm accelerating the convergence process. The convergence properties of the multiple-training LMS algorithm are also analyzed. We prove that the multiple-training LMS algorithm can converge regardless of its initial value and derive closed-form expressions for the weight error vector power. We further take advantage of the IS-136 downlink slot format and divide a slot into two subslots. Bidirectional processing is then applied to each individual subslot. The proposed LMS-based DFE has a low computational complexity and is suitable for real-world implementation. Simulations with a 900-MHz carrier show that our algorithm can meet the 3% bit error rate requirement for mobile speeds up to 100 km/hr     

A systolic array realization of the adaptive decision feedback equalizer

This paper presents a systolic array architecture for the adaptive decision feedback equalizer. The design is based on an algebra developed earlier by Kung and Lin (Proceedings of the Conference of Elliptic Problem Solvers, Monterey, CA, January 1983; Research Report CMU-CS-84-100, Department of Computer Science, Carnegie-Mellon University, Pittsburgh, PA, April 1983.) and is largely made up of two basic processing cells that are computationally equivalent and simple to realize. To maintain accuracy of the algorithm, the array needs to be operated by a clock with a speed twice of that the input. The increase in clock speed can, however, be exploited to reduce the total number of adders and multipliers by about 50%.