二进制域上椭圆曲线加密核的设计

为了提高椭圆曲线加密速度,介绍椭圆曲线密码体制发展优势,确定了椭圆曲线加密系统的体系结构,对二进制域上的加法、平方、乘法和逆运算用最新研究成果做了硬件设计并用Verilog实现,在这些底层运算基础上完成标量乘控制,实现了标量乘运算,最终实现椭圆曲线加密和解密的功能.在验证中编写验证模型和验证平台,对设计进行了功能验证并做了覆盖率统计,功能验证结果正确,覆盖率达到100%.对椭圆曲线加密核进行了逻辑综合和门级仿真,综合结果表明该核的运算频率可达125 MHz,门级仿真结果与功能仿真结果相同.     

调试功能仿真及验证平台设计

本文档针对ARM CPU芯片,介绍了支持双核CPU芯片调试功能仿真平台和验证平台的设计及实现方法.调试功能仿真平台主要由验证脚本和Debug Driver程序组成;调试功能验证平台是基于仿真平台进行设计,直接使用仿真平台的Debug Driver程序,由MCU中验证程序替代仿真验证脚本的功能,使用验证设计更加灵活、全面...     

八通道多协议串行通信控制器的功能验证

超大规模集成电路芯片的验证是一项复杂的任务,占据了整个芯片设计工作量的70%.实现了一款八通道多协议串行通信控制器芯片的功能验证,介绍了基于总线功能模型验证平台的建立方法,并根据此芯片的设计特点,研究了该芯片的验证策略,设计了验证平台,同时完成了芯片的后仿真和样片测试.实践证明,该验证策略具有较高的功能覆盖率,验证平台具有较好的复用性,对同类具有复杂通信协议电路的功能验证有一定的参考价值.     

基于SPARC V8的事务级SoC验证平台设计

针对片上系统SoC架构设计和嵌入式软件开发的需求,采用事务级建模方法使用SystemC完成了基于SPARC V8的事务级SoC验证平台的设计.为降低设计复杂度和提高仿真速度,基于解释-执行技术完成SPARC V8处理器指令精确事务级模型建模,并利用SystemC中的分层通道机制完成AMAB总线、中断控制器、UART、定时器等设备的事务级建模.完成事务级SoC验证平台的构建后,使用测试基准程序组Mibench对该验证平台的功能和仿真速度进行了验证.仿真结果证明了其功能正确,并且仿真速度相对于RTL SoC验证平台有大幅度的提高.     

一种快速验证FPGA互连线连接正确性的方法

随着FPGA规模的不断增大,互联线验证变得越来越困难。传统互连线验证采用功能仿真的方法,具有仿真速度慢、覆盖率低等不足。基于互连网络比对,设计了一种快速验证FPGA互连线连接正确性的方法。相对于功能仿真验证,该方法可以快速完成FPGA互连线连接正确性的验证,覆盖率高达100%,在保证互连正确的前提下,极大地缩短了设计时间。     

电子对抗装备数字仿真验证系统的实现

随着新形势下军事斗争的发展,为了尽快实现装备研制、验证手段数字化,工作全要素、全流程管理数字化,需要构建电子对抗装备数字仿真验证系统,为电子对抗装备的设计验证提供技术支撑.根据装备仿真验证的需求,设计研制了基于高层体系结构的电子对抗装备数字仿真验证系统,设计满足系统功能需求的软硬件体系结构和技术体系结构.     

PON结构航空总线协议芯片仿真验证方法

针对基于PON结构的FC_AE航空总线协议芯片的验证需求与功能特性,提出了一种基于RTL级组网功能仿真验证的方法,阐述该方法下仿真验证平台测试用例模块、参考模型模块、结果检测器模块、验证平台整合模块的实现原理,最后,采用该方法搭建了FC_AE协议芯片的仿真验证环境,完成该芯片的仿真验证.该方法基于多种语言自动化验证平台,可从系统级与芯片级双通道验证芯片功能,有效的提高了验证效率,缩短了整个设计验证周期,为芯片的成功投片提供了可靠的保证.     

LED驱动控制芯片的ASIC研究与设计

实现了一种LED驱动控制专用集成电路的前端设计.整个设计采用"自顶向下"的设计方法,首先进行行为级设计及功能验证和仿真,然后手工合成门级电路,并将设计的门级电路进行逻辑验证和仿真.通过对整个系统的仿真与验证,该电路具有功耗低、可靠性高、集成度高的特点,可以应用在VCR,VCD,DVD以及家庭影院等产品的显示屏驱动.     

一种飞机外挂物管理系统仿真设计

为了实现对飞机外挂物的智能管理仿真,采用面向对象的设计方法,将系统仿真建模、实验运行、设备控制和结果分析等功能融为一体,设计一种飞机外挂物管理仿真系统.该仿真系统集外挂物管理仿真、操作过程仿真、故障分析仿真和系统检测仿真等功能为一体,实现了外挂物管理的全数字仿真.详细讨论了该仿真系统的功能、组成、设计特点以及具体的硬件和仿真软件的实现方法.该系统可应用于综合航电仿真系统试验,验证系统的可行性与正确性.     

SoC设计刺激功能验证平台需求

随着设计复杂度的增加,以及SoC应用的普及,功能验证的重要性在日益增加.传统的基于仿真的验证需要数百万的测试向量来验证一个行为,而且仿真一般都处于系统集成完成后,因而设计返工次数多,验证的可靠性不能保证.     

Domain Coverage Metric for SoC Validation

The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface （VPI） and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.     

Design, Analysis, and Development of Novel Three-Dimensional Stacking WLCSP

A robust and rapid development procedure for a novel three-dimensional stacking wafer level chip-scaled packaging (3DS-WLCSP), emphasizing the finite-element parametric analysis and experimental validation, is disclosed herein. This design procedure is comprised of the fundamental validation of conventional wafer-level chip-scaled packaging (WLCSP), design methodology development of the test vehicles and then the fabrication of the proposed 3DS-WLCSP structure. Based on the validation of the conventional WLCSP measurement and experiment, a reliable finite-element model can be achieved. However, in order to reduce the product design period, a simplified Glass-WLCSP is chosen as the test vehicle in the parametric design/validation procedure. Through the parametric analysis, one can obtain robust design parameters. Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters.     

基于APTIX设备实现对数字系统的硬件加速验证

随着硬件描述语言(HDL)的发展,数字系统日趋复杂,对其进行验证需要很长时间,根据近年来的统计,对数字系统设计进行测试验证所花的时间占整个设计过程的60%以上.但是现在许多可编程逻辑器件(PLD)厂家都能够提供相关电子设计自动化(EDA)软件来完成对数字系统的快速验证,其中APTIX公司的设备是价格低、验证速度快、基于层次化和模块化的验证平台.文中以APTIX设备为开发环境,应用硬件加速验证的方法来实现对数字系统的快速验证.     

Development of a 50,000-gate programmable logic device for gate array prototyping

Systems designers want the cost and integration benefits from custom-logic solutions, but must mange the risk and cost of design errors. Several strategies have evolved to address this problem, with the two most common being design simulation, where a software model of the design is tested with simulated test vectors in an attempt to find error conditions, and emulation, where a hardware model of the design is tested with the same vectors, to attempt to find any errors. The principle difference between the two validation methods is how quickly they can identify errors in a design.     

Design of concurrent error detectable current-mode A/D converters for real-time applications

Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques eliminate errors traditionally associated with analog circuits. For real-time applications, however, it is rather difficult to achieve validation of the data generated from analog-to-digital (A/D) converters in the presence of faulty switching element(s). Conventionally, the validation is accomplished by using a high resolution and high accuracy D/A converter and a window comparator; i.e., the validation must highly depend on the reliability of both the D/A converter and the window comparator. In this paper, a novel current-mode A/D converter design with concurrent error detection (CED) capability is presented. The A/D converter does not need well-matched components and high-gain amplifiers. Results show that the proposed design can detect all the transient faults and most of the permanent faults. The proposed design allows users to easily switch to the normal operation mode where CED capability is not used, without causing any performance degradation.     

MMV: A Metamodeling Based Microprocessor Validation Environment

With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges. The systematic validation approach starts with defining the correct behaviors of the hardware and software components and their interactions. This requires new modeling paradigms that support multiple levels of abstraction. Mutual consistency of models at adjacent levels of abstraction is crucial for manual refinement of models from the full chip level to production register transfer level, which is likely to remain the dominant design methodology of complex microprocessors in the near future. In this paper, we present microprocessor modeling and validation environment (MMV), a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage, and test generation tools. We illustrate the functionalities in MMV by modeling a 32-bit reduced instruction set computer processor at the system, instruction set architecture, and microarchitecture levels. We show by examples how consistency across levels is enforced during modeling and also how to generate constraints for automatic test generation.     

Modelsim与MATLAB/Simulink联合仿真技术研究及应用

由于MATLAB/Simulink本身就是一款优秀的系统建模和算法仿真工具,Modelsim是国内最为常用的HDL仿真工具,利用Link for modelsim使Modelsim与Simulink协同工作,使得算法设计和验证在同一款软件中完成。避免了不同开发环境下的兼容性问题,极大地简化了设计的复杂度,加快了开发进程。提出利用基于模型的设计方法,可以将算法与硬件实现联合起来,对于算法的开发以及后期硬件实现都会带来极大的方便。详细介绍了Modelsim与MATLAB/Simulink联合仿真的接口技术、模型的搭建,以及通过利用16 QAM调制与解调的应用实例来验证系统的正确性。     

网络工程专业实验教学模式探索

针对目前网络工程专业实验教学中存在的困难,我们提出了基于GNS3的网络工程专业实验教学模式.该模式充分利用GNS3、VMware等软件来虚拟主机和网络设备,可以完成大部分网络类课程的验证性和设计性实验,并可以作为学生进行研究性实验的平台.该教学模式可以突破传统实验环境在时间和网络设备上的限制.     

宽禁带半导体器件环境适应性验证技术

应用验证是新型元器件走向实际工程应用必不可少的关键环节。从实际工程应用角度出发,给出了宽禁带半导体(SiC/GaN等)微波功率器件环境适应性验证过程中的验证分级(解决及时发现问题与验证周期、费用矛盾)、验证载体与工程应用统一性设计(器件研制源于工程、用于工程)、验证数据的可对比性设计(验证环节可追溯)方法及相关分析(指导工程设计),为宽禁带半导体微波功率器件的工程化研制提供数据支撑。文中的试验数据和设计思想可作为其他相关工程设计参考。