Extensive electrical and thermal characterization of an MCM-Dtechnology

In this paper, it is shown the work carried out on thermal characterization of the main materials employed in the deposited-type multichip module (MCM-D) technology. In this technology, silicon chips are mounted onto a silicon substrate by a flipchip technique. The substrates can be either passive with interconnection lines, Rs, Cs, and Ls or active with complementary metal oxide semiconductor (CMOS) technology cells. The metals used in this technology are aluminum for interconnection purposes, tantalum silicide for making resistors and a multilayer of wettable metal for solder connection. Measurements of sheet resistance and contact resistance versus temperature in the range of -28°C to 100°C of the metals used in the technology are shown. A set of classic test structures such as Kelvin contacts, cross bridge resistors (CBR), and Van der Pauw structures have been used for this purpose as well as a new Kelvin-like structure to test the contact resistance of the Flip Chip connection through the ball. This structure has been proven to be very sensitive allowing the measurement of changes in ball resistance in the range of mΩ. A thermal model of the MCM package has been obtained, taking into account all the thermal resistances added by this kind of package     

MCM-D技术电热特性综述

本文主要说明了淀积型多芯片组件(MCM-D)技术所使用的主要材料的热特性。此技术采用倒装片技术把硅芯片安装到硅基板上。阐述了薄膜电阻和接触电阻的测量与所使用金属的温度范围-28℃-100℃的比较。一套典型的试验结构诸如开尔文接触、横桥电阻(CBR)及Van der Pauw 结构不仅已用于此技术,而且为了测试通过球倒装片连接的接触电阻,采用一新的开尔文式结构。已获得MCM封装的热模型,并考虑由此类封装增加的所有的热电阻。     

Reliability evaluation of a silicon-on-silicon MCM-D package

This paper presents the results of reliability testing on a multichip module technology with active silicon substrates. The modules use flip-chip technology to attach silicon chips to the active substrate and this assembly is then packaged into a plastic ball grid array package. Performance was evaluated using two custom designed test chips incorporating thermal, thermomechanical, electrical and reliability test structures. A rigorous environmental test sequence including temperature, cycling, humidity, highly accelerated stress test and power cycling were carried out on the demonstrators. A full destructive physical analysis was then performed, consisting of die/substrate shear, wire bond pull tests and microsectioning.     

MCM基板互连测试的单探针路径优化研究

针对MCM基板互连测试所采用的单探针技术,本文提出一种基于蚁群算法的单探针路径优化算法,通过设定合适的规则,引导探针的移动,缩短探针移动的距离,达到减少测试时间提高MCM生产效率的目的.从基于MCM标准电路的仿真结果看,采用蚁群算法得到的探针测试路径长度远远优于其它算法所得到的.     

AlN多层基板的研制

MCM技术推动了现代微电子技术迅猛发展,已广泛应用于各种通讯系统的收发组件之中。AIN基板作为MCM技术多层基板主流之一,由于其高热导率、与硅片匹配的热膨胀系数、高介电常数、兼容各种芯片组装工艺的优点,在各个领域均获得了广泛的应用。文章结合一个微波组件AIN基板的研制,阐述了在AIN基板研制过程中解决的工艺难点,如粉料配制、流延、层压、烧结等,对研制的AIN基板进行了物理性能与电性能测试,结果表明AIN基板完全可以满足大功率毫米波／微波组件的实用化要求。     

Enhanced solder joint bonding strength of electronic packaging with electrowetting effect

This paper reports a novel method to enhance solder ball or solder ring bonding strength by using electrowetting-on-dielectric (EWOD) effect. With a low melting point, the metal Sn has been widely used in electronic packaging technology. Since Sn will be molten into liquid when the temperature is increased above the melting point, the method for treating liquid can be herein employed. Contact angle of the molten Pb-free balls or ring structure on silicon substrate have been experimentally changed by applying electric field across the thin dielectric film between the molten solder and the conductive silicon substrate. The contact area between the solder and the substrate is enlarged due to the decrease of the contact angle. Our testing results on the EWOD enhanced packaging structures of solder balls, flip-chip and solder ring hermetic package generally show about 50% enhancement in bonding shear strength. The significantly enhanced solder link bonding strength is hopeful for improving packaging reliability and is promising to be used in high performance silicon based electronic or microelectromechanic SiP (system in package) technologies.     

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.     

MCM封装技术中的基板设计与分析

通过采用多芯片组件封装技术,将6种由不同集成电路工艺实现的不同类型的芯片集成在单个封装内,简化了系统设计,实现了产品小型化的目标。同时,还详细给出了Zeni EDA工具下的MCM基板设计流程以及MentorPCB环境下的多芯片组件热分析方法。     

Monolithic InGaAsP optoelectronic devices with silicon electronics

The interface between optoelectronic devices and microelectronic circuits is the crucial component in the further development of optical communications, calling for inexpensive mass-produced solutions. We present a procedure for how these diverse elements can be monolithically integrated. A stringent requirement is the compatibility with existing fabrication techniques of microelectronic circuits in silicon. We demonstrate the feasibility of our method by the monolithic integration of a photodetector, based on InGaAs-InP, with a three-stage MOS amplifier on a Si substrate in (100) crystallographic orientation. Basic performance figures (dark current, sensitivity) are comparable to those obtained with test structures on the native InP substrate. We show that the developed technologies can be extended to light-emitting diodes and laser structures displaying efficient electroluminescence     

Status and trends of silicon RF technology

The current research and development activities in silicon radio-frequency (RF) technologies are first reviewed, accompanied by an illustration of the most pronounced shortcomings of conventional silicon technology in the integrability of RF functions at high GHz frequencies. In the discussion on active RF devices mainly CMOS is investigated due to great interest in this mass-production technology. Issues related to the integration of spiral inductors on silicon are addressed, stressing in particular the difficulty of RF substrate potential definition. Silicon micromachining techniques are highlighted as potential solutions to the integration of RF passives and to reduce substrate losses and cross-talk on silicon. It is explained that micromachining techniques are the best introduced to the silicon mainstream by using post-processing and minimum process complexity.     

Extension of a multilayer interconnection technology in MCM-Si with opto-electronic facilities

The increasing I/O-density of today’s packages is dealt with by using multilayer modules. Since there is also a trend towards faster interconnections by using optics, the extension of the interconnection module with V-grooves is in high demand. This paper reports on the electro-optical extensions of an earlier developed standard MCM-Si technology (Lernout et al., Journal of IMAPS (Europe) 1998; 15(1): 39–42; Ref. 1). The technology aspects of this standard MCM-Si technology are presented.The extended thin-film multilayer module is built up using two metal and three insulator layers. Additionally an implementation with low TCR resistors (NiCr) can be made. Fiber holding structures, namely V-grooves, are created into the bulk (100) silicon substrate by means of an anisotropic etching, performed in aqueous KOH. A passivation layer of silicon nitride, optimised towards low silicon content, served as protection mask during the KOH etching. The compatibility of this aggressive wet etching step with other processing steps is discussed. As for the insulators in the multilayer module, these high quality PECVD (Plasma Enhanced Chemical Vapour Deposition) layers are optimised towards low stress content and uniformity.Subsequently, the use of this interconnection substrate as a motherboard in multichip modules (MCM) is considered. The extension of the motherboard with V-grooves makes it possible to integrate opto-electronic (O/E) components, fibers and electronics on the same MCM-Si. Some of the major advantages are: low cost solution (saving non-used silicon area), compact assembly (carriers of fibers integrated with electronics), ability to reach higher frequencies (shorter interconnection distances),… Also low coupling losses between laser and fiber are achieved: the accuracy of V-grooves in silicon permits to place the fiber with high precision, and the self-aligning property of solder assures the control over the flip-chip (FC) mounted O/E-components (e.g. laser diodes).     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件（3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机（FR-4）基板,通过板上芯片（COB) 、板上倒装芯片（FCOB) 、球栅阵列（BGA）等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术（SMT）兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

Silicon on sapphire CMOS for optoelectronic microsystems

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues     

System on Wafer: A New Silicon Concept in SiP

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.      

Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency.     

Auto THERM在MCM热设计中的应用

针对一个基于硅基板的MCM电路建立了两种不同芯片布局的有限元热分析模型。利用热场分析理论并采用AutoTHERM软件,对两种布局条件下的温度场分布进行了仿真与分析。结果表明:不同的芯片布局导致温度场分布不同,两种方案的最高温度之差为6℃;将功率器件直接置于框架角落,而其余器件分布在硅基板上,可有效地减弱热耦合现象并使最高温度显著降低。该MCM在25℃下工作1h,温升小于10℃,满足使用要求。     

多芯片组件基板单探针测试路径的二次优化

基于模拟退火算法给出了一种可用于MCM互连基板单探针测试的二次优化方法,即采用模拟退火算法对启发式算法获得的MCM互连基板单探针测试路径进行二次优化改进.模拟结果显示,所提方法与已有的启发式优化算法相比较,对单探针路径的优化最高可达90.2%,可以有效地降低多芯片组件互连基板单探针测试的成本.     

Recent progress in bipolar transistor technology

Recent developments in high speed silicon bipolar device technologies are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. Double polysilicon bipolar device structures, in particular, have made it possible both to form shallow junctions and to reduce device dimensions. Recent progress of silicon bipolar transistor technology using SiGe and the use of the SOI technology to obtain high speed operations are also reviewed     

Packaging technology for high performance CMOS server FujitsuGS8900

Advanced packaging technologies for CMOS based high performance Fujitsu Global Server GS8900, released in late 1999, are introduced in this paper. Extending a new standard for technological leadership among large-scale enterprise servers, the GS8900 broke the 2000 MIPS barrier in performance for the first time by taking advantages of Fujitsu advanced 0.18 μm copper wiring process and chip/MCM/system packaging capabilities, delivering a doubled performance in comparison to its predecessor. The packaging technologies are uniquely characterized in several aspects. First, the high density stacked via type MCM-D technology features four pairs of CPU tightly coupled multiprocessor and large capacity second caches, the maximum processor terminal count is more than 10,000. The processors are wired onto a multilayer thin film MCM substrate with 153 μm pitch high-density area array lead-free bumps. Secondly, maximum four CPU-MCMs, including 16 CPU processors, and 64 GB main memory modules are mounted on one multilayer system board of high frequency transmission properties. Each MCM is held through a high-density ZIF connector of around 3000 I/Os in a 1.27 mm pitch full matrix, which is assembled on the system board with lead-free solders. Thirdly, advanced cooling technologies are developed for improving the system performance and reliability     

A micromachining technology for integrating low-loss GHz RF passives on non-high-resistivity low-cost silicon MCM substrate

A micromachining technology for integrating high-performance radio-frequency (RF) passives on CMOS-grade low-cost silicon substrates is developed. The technology can form a thick solid-state dielectric isolation layer on silicon substrate through high-aspect-ratio trench etch and refill. On the non-high-resistivity but low-loss substrate, two metal layers with an inter-metal dielectric layer are formed for integrating embedded RF components and passive circuits. Using the technology, two types of integrated RF filters are fabricated that are band-pass filter and image-reject filter. The band-pass filter shows measured minimum insertion loss of 3.8 dB and return loss better than 15 dB, while the image-reject filter exhibits steeper band selection and achieves better than −30 dB image rejection. A 50 Ω co-planar waveguide (CPW) on the substrate is also demonstrated, showing low loss and low dispersion over the measured frequency range up to 40 GHz. The developed technology proves a viable solution to implementing silicon-based multi-chip modules (MCM) substrates for RF system-in-package (RF-SiP).