An NMOS input merged bipolar/sidewall-MOS transistor with a bypasssidewall MOS transistor (NBiBMOS transistor)

The concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (V_CE or V_DE) is less than the turn-on voltage of the n-p-n bipolar transistor (V_BE=~0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy ~1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

RF small signal avalanche for bipolar transistor circuit design: Characterization, modeling and repercussions

In the face of increasing demands for high frequency and high output power of modern bipolar transistor circuits, electronic circuit designers are exploring regimes of transistor operation that meet both requirements and enter RF regimes, where impact ionization is significant. The present paper addresses AC/RF avalanche characterization techniques. Repercussions of avalanche breakdown on some important transistor properties like unilateral power gain and the stability factor are introduced and demonstrated by measurements on modern industrial devices. On the basis of theoretical considerations and compact model simulations it is shown when avalanche can be expected to have significant impact on AC performance of bipolar transistors.     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

1.0-µm n-well CMOS/bipolar technology

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n⁺-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n⁺-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

Evidence of optical generation of minority carriers from saturated MOS transistors

Minority carrier injection into the substrate by a MOS transistor operating in saturation presents a reliability problem in dynamic memory circuits such as RAM's and CCD's. The effect has been studied by measuring the substrate and drain currents of stressed transistors as a function of gate and drain voltages, firstly by the accumulation of minority carriers in a charge coupled device, and secondly by the direct detection of light from the drain region of a transistor. These results suggest that light emission associated with multiplication in the drain region is more important than the secondary impact ionization mechanism in the generation of minority carriers.     

A better bipolar transistor for wireless ICs

As the world unwires, the market for wireless communication chips has begun to soar. Now, a breakthrough by IBM researchers promises to unleash a new generation of low power wireless communication ICs by solving a problem that has plagued semiconductor specialists for years. The problem revolves around the so-called mixed signal chips, which contains both ordinary field-effect transistors and bipolar transistors. This article presents a better bipolar transistor for wireless communications ICs. It also demonstrates the first structure to allow high-speed, low power bipolar transistor on the same chip with the fastest, lowest power CMOS circuits. The fastest bipolar transistors contain germanium in their bases, which lets them run in excess of 350 GHz, which is much faster than the ordinary silicon bipolar devices.     

A closed-form delay expression for digital BiCMOS circuits withhigh-injection effects

A non-iterative formula is derived for calculating the delay time of digital BICMOS circuits with their bipolar transistors operating in high-current regime. Effects such as the base transit-time increase of minority carriers and the decrease of the current gain of the bipolar transistors are all incorporated in the model. This model can be used to investigate the effects of most device parameters such as transistor sizes and external loading on the performance of the circuits without resorting to any iterative procedures. This simplified model compares well with the original model to 10% over a wide range of operating conditions, and is especially accurate for situations where base widening affects the bipolar transistors     

A latch phenomenon in buried N-body SOI NMOSFET's

The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V_GS is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current     

A fully complementary BiCMOS technology for 10 V mixed-signalcircuit applications

A 10 V fully complementary BiCMOS technology, HBC-10, has been developed for high speed, low noise and high precision mixed signal system integration applications. In this technology, two varieties of CMOS transistors have been implemented for 10 V analog and 5 V digital applications. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS transistors with a lightly doped drain extension added to the NMOS structure to achieve device lifetime in excess of 10 years. A gate oxide thickness of 18 nm is used for 5 V CMOS logic circuits. These transistors are specially architected so that they may also serve as analog transistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed by use of a double diffused drain structure. The active devices are isolated by a fully recessed 1.5 μm oxide grown under high pressure conditions. Use of high pressure steam, plus combining diffusion operations where possible, results in a low overall thermal budget. This allows the up-diffusion of buried layers to be minimized so that a thin, 1.6 μm epitaxial silicon layer is sufficient to support 10 V bipolar transistors. The resultant vertical PNP and NPN transistors are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more than 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxide-polysilicon capacitor and trimmable thin film resistor are integrated into this process. This wide variety of passive and active components is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operations is 23, which includes double layer metallization     

CMOS-compatible lateral bipolar transistor for BiCMOS technology.II. Experimental results

For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of h_FE, BV_CEO, R _CS, f_Tmax, and r_bb', are 20, 7 V, 50 Ω, 6.3 GHz, and 450 Ω, respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors     

Fast-switching and shallow saturation bipolar power transistorsusing corrugated base junctions

A fast-switching and shallow saturation bipolar power transistor fabrication technology using corrugated base junctions, which does not require additional process steps, is proposed in this paper. Computer simulation shows that less excess minority and majority carriers stored in the base and the collector drift region cause the shallow saturation phenomena of the corrugated base transistors at the conduction stage, and that the corrugated base transistors have lateral built-in electric fields under the base electrode, which accelerate the movement of the minority carriers from the bulk to the surface and promote the recombination of excess electrons and holes in the base region. The turn-off times and the saturation voltages between the collector and the emitter are studied systematically as a function of the base masking oxide widths of the corrugated base region, which agree well with the simulation results     

A four-quadrant current multiplier/divider cell with four transistors

We propose a four quadrant six transistor current multiplier cell based on the translinear principle. The cell is further modified by using resistive feedback to remove two PNP transistors hence reducing the total transistor count to four NPN transistors only. This not only eliminates the problem of mismatch between the two transistor types but allows the cell to operate both as a current multiplier/divider depending on the resistive feedback ratio. The modified cell can also multiply mixed current/voltage signals and operates equally well with NMOS transistors instead of bipolar ones. Experimental results using discrete transistors confirming the correct operation of the cell are provided.     

Derivation of low-power first-order low-pass,high-pass and all-pass filters

In this letter, a new voltage-mode (VM) configuration for providing low-power and simultaneous realization of first-order low-pass, high-pass and all-pass filters is presented. The output of the all-pass filter is taken differentially. The proposed circuit contains low number of components, i.e., only two NMOS transistors, a floating battery, a grounded capacitor and a floating resistor. Adding two NMOS transistors to the proposed circuit it is modified as an all-pass filter with a single-ended output. The main advantage of the presented circuits in comparison with other counterparts is their extremely low power dissipation. Moreover, the floating resistor can be replaced with an additional NMOS transistor in triode region to provide electronic tunability. Simulation results using SPICE program are given to demonstrate the performance of the proposed circuit.     

N-Channel MOSFETs with WSi2gate

Tungsten silicide gate depletion- and enhancement-mode NMOS transistors were fabricated. The transistor characteristics revealed the excellent compatability of WSi2as gate electrode for MOS integrated circuits. Electron mobility of channel at saturation were found to be 210 cm²/v sec for enhancement-mode transistor and 110 cm²/v sec for depletion-mode transistor.     

Study of the impact of hot carrier injection to immunity of MOSFET to electromagnetic interferences

This paper presents an original study about the effect of hot carrier injection stress on the DC offsets induced by electromagnetic interferences (EMI) on a nanometric NMOS transistor, which is one of the major sources of failures in analog circuits. Measurements and simulations based on a simple model (Sakurai–Newton model) of fresh and stressed transistors are presented and show significant variations of EMI-induced DC shifts of drain current.     

Photon generation in forward-biased silicon p-n junctions

Photons are generated by forward biasing a silicon p-n junction at 10^-5∼ 10^-4quantum efficiency through radiative recombination. At large distances from the forward-biased junction, leakage currents of magnitudes significant for some VLSI circuits can appear due to the substrate minority carriers generated by the photons. The effective decay length of the measured leakage current is about several hundred to one thousand micrometers. The effects of forward biasing an input node or a parasitic lateral bipolar transistor are, therefore, longer ranged than commonly assumed.     

Antiambipolar Transistor: A Newcomer for Future Flexible Electronics

An antiambipolar transistor exhibits a steep increase and decrease in drain current within a certain range of gate bias voltage. This unique feature is brought about by a partially stacked pn‐heterointerface formed around the center of the transistor channel. First, this review discusses recent topics related to the antiambipolar transistor, including the constituent materials, operation mechanism, and factors controlling device performance. Then, novel functional applications, such as optoelectronics and multivalued logic circuits, are introduced. The transistor channels of antiambipolar transistors consist largely of 2D atomically thin films or organic semiconductors. These materials are mechanically flexible. Therefore, antiambipolar transistors have the potential to enable advances to be made in the field of flexible electronics.     

Analysis of mesastable operation in RS CMOS flip-flops

An analysis of metastable operation in CMOS RS flip-flops is presented. An analytical formula for the flip-flop resolving time constant was derived using Shichman-Hodges model for NMOS and PMOS transistors. This formula, as related to the transistor dimensions, fabrication process parameters, and parasitic capacitance, uses proper transistor sizing to attain minimum flip-flop failure rate due to metastable operation. CMOS n-well, p-well, and twin-well flip-flop performance predicted analytically is also approved by SPICE level one simulation of transistor models. Real-time oscilloscope displays of metastable operation for two different CMOS RS flip-flop circuits are demonstrated.     

Design of Gate‐Ground‐NMOS‐Based ESD Protection Circuits with Low Trigger Voltage,Low Leakage Current,and Fast Turn‐On

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate‐triggered NMOS and a gate‐substrate‐triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn‐on speed. The proposed ESD protection devices are designed using 0.13 μm CMOS technology. The experimental results show that the proposed substrate‐triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn‐on time of 37 ns. The proposed gate‐substrate‐triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.