Electron mobility in ULSI MOSFETs: effect of interface traps andoxide nitridation

We provide a comprehensive set of electron mobility measurements at 300 K and 77 K on standard and N₂O-nitrided MOSFETs, with channel doping in the range 3.8×10¹⁷-1.25×10¹⁸ cm^-3. In such heavily-doped devices, the Fermi level always lies very close to the conduction band edge, where interface traps reach the highest density and the shortest lifetimes. We show that these traps contribute to the gate-channel capacitance, leading to a systematic overestimate of the channel charge. This effect has the largest impact precisely in the roll-off region of the mobility curves, which has been the subject of recent theoretical investigations     

Deep-level dominated current-voltage characteristics of buriedimplanted oxide silicon-on-insulator

Current-voltage characteristics of Au contacts formed on buried implanted oxide silicon-on-insulator (SOI) structures are discussed, which indicate that the dominant transport mechanism is space-charge-limited current (SCLC) conduction in the presence of deep-level states. The deep-level parameters, determined using a simple analysis, appear to be sensitive to anneal conditions used and subsequent processing. Silicon implanted with 1.7×10¹⁸ cm^-2 oxygen ions at 150 keV following a 1200°C anneal for 3 h shows deep level 0.37 eV below the conduction band edge with a concentration of unoccupied traps of ~ 2×10¹⁵ cm^-3 . In contrast, arsenic ion implantation, in the 1200°C annealed material with a dose of 1.5×10¹² cm^-2 at 60 keV and activated by rapid thermal annealing (RTA), introduces a deep level 0.25 eV below the conduction band edge with an unoccupied trap concentration of ~6×10¹⁷ cm^-2     

Counter-doped MOSFETs of 4H-SiC

In this paper, we investigate the effect of counter-doping of nitrogen at the channel region of epitaxial n-channel 4H-SiC MOSFETs on the channel mobility and the threshold voltage. From this study, we have found that the channel mobility steeply improves as the nitrogen dose increases. At a dose of 2× or 2.5×10¹² cm^-2 the enhancement MOSFET has achieved an effective channel mobility of 20 cm²/Vs or a field effect mobility of 38 cm²/Vs at a peak     

Polysilicon emitter p-n-p transistors

In-situ boron-doped polysilicon has been used to form the emitter in p-n-p transistors. Various polysilicon deposition conditions, interface preparation treatments prior to deposition, and post-deposition anneals were investigated. Unannealed devices lacking a deliberately grown interfacial oxide gave effective emitter Gummel numbers G_E of 7-9×10^-12s cm^-4 combined with emitter resistances R_E of approximately 8 μΩcm². Introduction of a chemically grown interfacial oxide increased G_E to 2×10 ¹⁴s cm^-4, but also raised R_E by a factor of three. Annealing at 900°C following polysilicon deposition raised G_E values for transistors lacking deliberate interfacial oxide to approximately 6×10¹³s cm^-4, but had little effect of G_E for devices with interfacial oxide. Both types of annealed devices gave R_E values in the range 1-2 μΩcm²     

Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO₂/SiC interface of 5 X 10¹⁸ and 1.5 X 10¹⁹ cm^-3 and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm²/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET.     

Effects of trap-state density reduction by plasma hydrogenation inlow-temperature polysilicon TFT

The reduction of trap-state densities by plasma hydrogenation in n-channel polysilicon thin-film transistors (poly-TFTs) fabricated using a maximum temperature of 600°C has been studied. Hydrogenated devices have a mobility of ~40 cm²/V×5, a threshold voltage of ~2 V, an inverse subthreshold of ~ 0.55 V/decade, and a maximum on/off current ratio of 5×10⁸. The effective channel length decreases by ~0.85 μm after a short hydrogenation which may be attributed to the activation of donors at trap states near the source/drain junctions. Trap-state densities decrease from 1.6×10¹² to 3.5×10¹¹ cm^-2 after hydrogenation, concomitant with the reduction of threshold voltage. Using the gate lengths at which the trap-state densities deviate from the long-channel values as markets for the leading edge of passivation, the apparent hydrogen diffusivity is found to be 1.2×10^-11 cm²/s at 350°C in the TFT structure     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

4H-SiC MOSFETs utilizing the H2 surface cleaningtechnique

The H₂ cleaning technique was examined as the precleaning of the gate oxidation for 4H-SiC MOSFETs. The device had a channel width and length of 150 and 100 μm, fabricated on the p-type epitaxial layer of 3×10¹⁶ cm^-3. The gate oxidation was performed after the conventional RCA cleaning, and H₂ annealing at 1000°C. The obtained channel mobility depends on the pre-cleaning process strongly, and was achieved 20 cm²/N s in the H₂ annealed sample. The effective interface-state density was also measured by the MOS capacitors fabricated on the same chips, resulting 1.8×10¹² cm^-2 from the photo-induced C-V method     

Electrical characteristics of MOSFETs using low-pressurechemical-vapor-deposited oxide

The electrical characteristics of MOSFETs and MOS capacitors utilizing thin (80-230 Å) low-pressure chemical-vapor-deposited (LPCVD) oxide films deposited at 12 Å/min are presented. MOSFETs using CVD oxides show good electrical characteristics with 70-90% of the surface mobility of conventional MOSFETs. The CVD oxides exhibit the same low leakage current and high breakdown fields as the thermal oxides, and significantly lower trapping and trap generation rates than thermally grown oxides. Interface state densities of ⩽3×10¹⁰ cm^-2 eV^-1 are obtained from CVD devices by using a short annealing in oxygen ambient following the deposition. These results indicate that these LPCVD oxide films may be promising dielectrics for MOS device application     

A semi-empirical model for the field-effect mobility ofhydrogenated polycrystalline-silicon MOSFETs

The quantitative relationship between field-effect mobility (μ _FE) and grain-boundary trap-state density (N_t ) in hydrogenated polycrystalline-silicon (poly-Si) MOSFETs is investigated. The focus is on the field-effect mobility in MOSFETs with N_t 1×10² cm^-2. It is found that reducing N_t to as low as 5×10¹¹ cm^-2 has a great impact on μ_FE. MOSFETs with the N_t of 4.2×10¹¹ cm^-2 show an electron mobility of 185 cm²/V-s, despite a mean grain size of 0.5 μm. The three principal factors that determine μ_FE, namely, the low-field mobility, the mobility degradation factor, and the trap-state density N_t are clarified     

A physically-based model of the effective mobility in heavily-dopedn-MOSFETs

We present a new analytical mobility model for channel electrons in heavily-doped MOSFETs biased from weak to strong inversion suitable for implementation in device simulation codes. The model accounts for the two-dimensionality of the electron gas and for the effect of charge trapping on the measurements and has been validated by comparing the theoretical curves with an extensive set of mobility measurements performed on devices with channel doping ranging from 3.8×10¹⁷ to 1.25×10¹⁸ cm^-3 over a wide bias and temperature range (141-400 K)     

New channel engineering for sub-100 nm MOS devices considering bothcarrier velocity overshoot and statistical performance fluctuations

We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity υ_e is not degraded at channel dopant density N_a lower than 1×10¹⁷ cm^-3, according to an experimental universal relationship between υ_e and the low field mobility. On the other hand, there is a most suitable N_a condition for suppression of statistical threshold voltage fluctuations. This most suitable N_a is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1×10 ¹⁷ cm^-3 in both cases. Therefore, this most suitable N_a condition is consistent with the above N_a condition for carrier velocity. Consequently, new N_a conditions for nano region devices are introduced in this study. N_a should be designed to be of the order of 1×10¹⁶ cm^-3 rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively     

Dependence of electron channel mobility on Si-SiO2interface microroughness

The effect of the Si-SiO₂ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH₄ OH in the NH₄OH-H₂O₂-H₂O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO₂ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm²/V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5×10¹⁷ cm^-3, i.e. the electron bulk mobility is 400 cm²/V-s. It goes down to 100 cm²/V-s when the interface microroughness exceeds 1 nm     

Back-gated buried oxide MOSFETs in a high-voltage bipolartechnology for bonded oxide/SOI interface characterization

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2×10¹²/cm² at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4×10¹⁰/cm² in the buried oxide     

10 A, 2.4 kV Power DiMOSFETs in 4H-SiC

We report the characteristics of large area (3.3 × 3.3 mm ²) high-voltage 4H-SiC DiMOSFETs. The MOSFETs show a peak MOS channel mobility of 22 cm²/V·s and a threshold voltage of 8.5 V at room temperature. The DiMOSFETs exhibit an on-resistance of 4.2 mΩ·cm² at room temperature and 85 mΩ·cm² at 200°C. Stable avalanche characteristics at approximately 2.4 kV are observed. An on-current of 10 A is measured on a 0.103 cm² device. High switching speed is also demonstrated. This suggests that the devices are capable of high-voltage, high-frequency, low-loss switching applications     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Enhancement mode InP MISFET's with sulfide passivation andphoto-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P₃N₅ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10⁴ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm ²/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×10¹⁴/cm² eV has been attained     

Electron velocity overshoot at room and liquid nitrogentemperatures in silicon inversion layers

Effective electron velocities in silicon MOSFETs exceeding the bulk saturation values of 10⁷ cm/s at room temperature and 1.3×10⁷ cm/s at liquid-nitrogen temperature are inferred. This conclusion suggests that electron velocity overshoot occurs over a large portion of the device channel length. To infer this phenomenon, submicrometer-channel-length Si MOSFETs with lightly doped inversion layers were fabricated. These devices have low field mobility of 450 cm²/V-s and showed only slight short-channel effects. Effective carrier velocities are calculated from the saturated transconductance g_m at V_DS=1.5 V after correction for parasitic resistances of source and drain     

Reduction of oxide charge and interface-trap density in MOScapacitors with ITO gates

The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps N_f and N _it, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240°C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950°C in N₂, followed by a 30 min anneal in N₂/20% H₂ at 450°C. Typical values obtained for N_it and N_f are 4.2×10¹⁰ cm^-2 and 2.8×10¹⁰ cm^-2, respectively. These values are further reduced to 1.9×10¹⁰ cm^-2 and ≲5×10⁹ cm^-2, respectively, by depositing approximately 25 nm polycrystalline silicon on the gate insulation prior to the deposition of ITO