High-speed buffer management for 40 gb/s-based photonic packet switches

We develop a method of high-speed buffer management for output-buffered photonic packet switches. The use of optical fiber delay lines is a promising solution to constructing optical buffers. The buffer manager determines packet delays in the fiber delay line buffer before the packets arrive at the buffer. We propose a buffer management method based on a parallel and pipeline processing architecture consisting of (log/sub 2/N+1) pipeline stages, where N is the number of ports of the packet switch. This is an expansion of a simple sequential scheduling used to determine the delays of arriving packets. Since the time complexity of each processor in the pipeline stages is O(1), the throughput of this buffer management is N times larger than that of the sequential scheduling method. This method can be used for buffer management of asynchronously arriving variable-length packets. We show the feasibility of a buffer manager supporting 128 /spl times/ 40 Gb/s photonic packet switches, which provide at least eight times as much throughput as the latest electronic IP routers. The proposed method for asynchronous packets overestimates the buffer occupancy to enable parallel processing. We show through simulation experiments that the degradation in the performance of the method resulting from this overestimation is quite acceptable.     

To Burst or Circuit Switch?

We develop, analyze and then numerically compare performance models of a fast-adapting and centrally controlled form of optical circuit switching (OCS) with a conservative form of optical burst switching (OBS). For the first time, we consider a unified model comprising both: edge buffers at which arriving packets are aggregated and enqueued according to a vacation-type service discipline with nondeterministic set-up times, together with a core network comprising switches arbitrarily interconnected via fibers to allow transmission of packets from an edge buffer to their desired egress point through use of a dynamic signaling process to establish a lightpath, and in the case of OCS, also acknowledge its establishment. As such, edge buffers dynamically issue requests for wavelength capacity via a two or one-way reservation signaling process. Previously analyzed models of OCS and OBS have either been for a stand-alone edge buffer or a core network without edge buffering. We compare OCS with OBS in terms of packet blocking probability due to edge buffer overflow and blocking at switches in the case of OBS; mean packet queueing delay at edge buffers; and, wavelength capacity utilization. Also for the first time, we derive the exact blocking probability for a multi-hop stand-alone OBS route, assuming Kleinrock's independence, which is not simply a matter of summing the stationary distribution of an appropriate Markov process over all blocking states, as shown to be the case for an OCS route.      

Synchronously Loaded Optical Packet Buffer

Synchronous optical packet buffering is demonstrated utilizing a fiber-based synchronizer with a photonic integrated circuit packet buffer. Asynchronously arriving packets are optically synchronized to a local frame clock and loaded synchronously into the optical buffer. The synchronizer is a four-stage design with a resolution of 853 ps and a dynamic tuning range of 12.8 ns. The optical packet buffer consists of an integrated 2 × 2 InP switch coupled to a silica-on-silicon 12.8-ns delay line. Packet recovery measurements of 40-B return-to-zero packets at 40 Gb/s show-error free performance for several combinations of synchronizer and buffer delays.     

Performance Evaluation of Single-Wavelength Fiber Delay Line Buffer With Finite Waiting Places

The performance of single-wavelength fiber delay line buffer with finite waiting places is evaluated in this paper. For Poisson arriving packets with arbitrarily distributed lengths, the generating function of delay time distribution can be derived from the quantized delay buffer model. Then queue length distributions, loss probability, and other important performance measures can be figured out. Specifically, two important cases of negative-exponentially distributed packet lengths and fixed packet lengths are considered and compared. The accuracy of the proposed approach is verified through simulation. It is also observed that the buffer system performs more effectively for the fixed-length packets.     

Performance of fiber delay‐line buffers in asynchronous packet‐based optical switching networks with wavelength conversion

A major challenge in asynchronous packet‐based optical networks is packet contention, which occurs when two or more packets head to the same output at the same time. To resolve contention in the optical domain, two primary approaches are wavelength conversion and fiber delay line (FDL) buffering. In wavelength conversion, a contending packet can be converted from one wavelength to another in order to avoid conflict. In FDL buffering, contending packets can be delayed for a fixed amount of time. While the performance of wavelength conversion and FDL buffering has been evaluated extensively in synchronous networks with fixed‐sized packets, in this paper, we study the performance of FDL buffers in asynchronous packet‐based optical networks with wavelength conversion. An analytical model is proposed to evaluate the performance in terms of packet loss probability and average delay. Extensive simulation and analytical results show that, with appropriate settings, FDL buffers can perform much better in switches with wavelength conversion than in switches with no conversion. Copyright © 2014 John Wiley & Sons, Ltd.     

Low-loss switching fabric design for recirculating buffer in WDM optical packet switching networks using arrayed waveguide grating routers

In this paper, we give a new switching fabric design for the recirculating buffer in optical packet switching networks. We note that since a packet to be buffered can be routed to any delay lines, the switching fabric connecting packets to the delay lines can be simplified. We give a design based on the arrayed waveguide grating router, and give a simple linear time-control algorithm for assigning buffer locations to the packets. To the best of our knowledge, this is the first switching fabric specifically designed for recirculating buffers which takes advantage of the fact that packets can be routed to any delay lines.     

A framework for fiber delay‐line buffers in packet‐based asynchronous multifiber optical networks (PAMFONET)

A major challenge in packet‐based optical networks is packet contention, which occurs when two or more packets are heading to the same output at the same time. To resolve contention in the optical domain, a fundamental approach is fiber delay‐line (FDL) buffering, in which packets can be delayed for a fixed amount of time. In the literature, the performance of FDL buffering has been studied extensively. However, most existing works are based on an assumption that there is only one fiber per link in the network. In this paper, we address the architecture and performance of FDL buffers in packet‐based asynchronous multifiber optical networks (PAMFONET), in which each link in the network may consist of multiple optical fibers. We propose a framework for FDL buffers in PAMFONET, in which we provide three essential architectures and corresponding packet scheduling policies. Extensive simulation results show that, with appropriate settings, the same number of FDLs can lead to better performance in multifiber networks than in single‐fiber networks. Copyright © 2011 John Wiley & Sons, Ltd.     

On spatially disjoint lightpaths in optical networks

Within the communication networks, a delayed constrained data packet is the one that will be dropped if not being served before a certain deadline time, which causes data packet loss affecting the quality of service (QoS). In this paper, we study the blocking probability and the mean delay of such delay constrained packets in an asynchronous single-wavelength optical buffer in optical packet switching networks, where the packet arrival process follows the Poisson process and the packet-length distribution is assumed to be general. We obtain the integral equations of the modeled system and the exact expressions of blocking probabilities and the mean delays. Numerical examples are provided to validate the results with interesting observations being highlighted.     

Store-and-Forward Buffer Requirements in a Packet Switching Network

Previous analytic models for packet switching networks have always assumed infinite storage capacity in store-store-and-forward (S/F) nodes. In this paper, we relax this assumption and present a model for a packet switching network in which each node has a finite pool of S/F buffers. A packet arriving at a node in which all S/F buffers are temporarily filled is discarded. The channel transmission control mechanisms of positive acknowledgment and time-out of packets are included in this model. Individual S/F nodes are analyzed separately as queueing networks with different classes of packets. The single node results are interfaced by imposing a continuity of flow constraint. A heuristic algorithm for determining a balanced assignment of nodal S/F buffer capacities is proposed. Numerical results for the performance of a 19 node network are illustrated.     

B—DMB快速分组交换机的性能分析

由于不能预先对进入B-DMB交换机的各分组进行调整,可能出现同一时隙有2个或2个以上的分组都要到达某一输出端的情形,因此在B-DMB交换机中不可避免地要加进一些缓冲器。本文对B-DMB交换机的输入、输出缓冲器长度和分组时延进行了分析和计算,得出了一些有用的结论。     

Scheduling algorithms for shared fiber-delay-line optical packet Switches-part II: the three-stage clos-network case

In all-optical packet switching, packets may arrive at an optical switch in an uncoordinated fashion. To prevent packet loss in the switch, fiber delay lines (FDLs) are used as optical buffers to store optical packets. However, assigning FDLs to the arrival packets to achieve high throughput, low delay, and low loss rate is not a trivial task. In the authors' companion paper, several efficient scheduling algorithms were proposed for single-stage shared-FDL optical packet switches (OPSs). To further enhance the switch's scalability, this work was extended to a multistage case. In this paper, two scheduling algorithms are proposed: 1) sequential FDL assignment and 2) multicell FDL assignment algorithms for a three-stage optical Clos-Network switch (OCNS). The paper shows by simulation that a three-stage OCNS with these FDL assignment algorithms can achieve satisfactory performance.     

Approximate Modeling of Optical Buffers for Variable Length Packets

This paper addresses the problem of dimensioning buffers realized by means of fiber delay lines in optical routers able to switch packets that have variable length and are sent asynchronously on the optical links. The optical buffer is analyzed focusing on the different behavior of a delay buffer and an electronic memory. The role of the time unit of the fiber delay lines is discussed, showing that it is a crucial parameter to determine the queuing performance. The paper presents two approximate analytical models that can be used both for analysis and engineering of the optical buffer and in particular to dimension the buffer time unit in an way that is optimal with respect to packet loss probability. The first model is based on an infinite queuing approximation. It is not very accurate and is valid for a limited set of values of the traffic load, but is extremely simple. The second model is based on a finite queuing approximation. It is more complex but more accurate and is valid for any value of traffic load. The accuracy of the models is compared with simulation and their range of applicability purposes is discussed.     

Packet scheduling algorithms and performance of a bufferedshufflenet with deflection routing

In a multihop network, packets go through a number of hops before they are absorbed at their destinations. In routing to its destination using minimum path, a packet at a node may have a preferential output link (the so-called “care” packet) or may not (the so-called “don't care” packet). Since each node in an optical multihop network may have limited buffer, when such buffer runs out, contention among packets for the same output link can be resolved by deflection. In this paper, we study packet scheduling algorithms and their performance in a buffered regular network with deflection routing. Using shufflenet as an example, we show that high performance (in terms of throughput and delay) can he achieved if “care” packets can be scheduled with higher priority than “don't care” packets. We then analyze the performance of a shufflenet with this priority scheduling given the buffer size per node. Traditionally, the deflection probability of a packet at a node is solved from a transcendental equation by numerical methods which quickly becomes very cumbersome when the buffer size is greater than one packet per node. By exploiting the special topological properties of the shufflenet, we are able to simplify the analysis greatly and obtain a simple closed-form approximation of the deflection probability. The expression allows us to extract analytically the performance trend of the shufflenet with respect to its buffer and network sizes. We show that a shufflenet indeed performs very well with only one buffer, and can achieve performance close to the store-and-forward case using a buffer size as small as four packets per node     

The Behavior of a Finite Queue with Batch Poisson Inputs Resulting from Message Packetization and a Synchronous Server

This paper studies the behavior of a packet switch which provides finite waiting space and receives packetized messages. The arrivals of the messages constitute a Poisson process. Each message consists of a random number of packets. The number of packets contained in a message is assumed to be an integer-valued random variable which may follow any arbitrary probability distribution. All packets residing in the buffer receive service from a single output transmitter operating synchronously at a constant rate. Each packet receives the same fixed service time from the transmitter and then leaves the system. Upon the arrival of a message, if the remaining buffer space is not enough to accommodate all packets of the message, then the entire message is completely rejected. Results such as message blocking probability, packet blocking probability, throughput, and mean delay have been obtained. Two different approaches, minislot approximation and the application of the residue theorem, are used to obtain these results. Especially, this combinatorially very complex problem is successfully solved by the residue theorem in a recursive manner. These results are useful in evaluating the performance of a packet switch. They are also useful for design purposes.     

Designing an Optimal Scheduler Buffer in OBS Networks

In this paper, we dimension a buffer in which headers are enqueued before processing in an optical burst switching (OBS) network. For the first time, we develop and analyze a unified OBS model comprising a set of homogeneous and independent edge buffers that feed bursts to a standalone link and their headers to a scheduler. Packets arrive at each edge buffer and are assembled into bursts, after which they are transmitted on a wavelength channel if their corresponding headers are successfully processed. In a case study, we demonstrate numerically that an optimal scheduler buffer size may exist and depends on the number of packets comprising a burst and the size of an edge buffer. We also show that packet blocking probability can be minimized using a simple rule of thumb for determining the optimal size of a scheduler buffer and the number of packets comprising a burst. All our analytical results are validated by way of simulation.      

Scheduling scheme using Look-ahead Buffer and Loop-back Buffer in Two-stage variable optical packet switch

Programmable variable delay lines have been developed, so as to delay packets in variable durations by combining several lengths of Fiber Delay Lines (FDLs) in optical packet switch. In practice, Two-stage variable optical packet switch with this programmable variable delay lines has been proposed. This switch has two buffers. The one is the programmable variable delay lines (Look-ahead Buffer). The other is the fixed FDLs that re-input a packet from the output to the input (Loop-back Buffer). The switch can foresee following packets and avoid contentions effectively by using two buffers. However, existing studies only focus on the Look-ahead Buffer. Intelligent usage of the Loop-back Buffer is actually out of concern. This paper proposes a sophisticated scheduling method in the Two-stage switch. The proposed method controls both the Look-ahead Buffer and the Loop-back Buffer cooperatively and improves the utilization of the switching process. The proposed method uses the Loop-back Buffer adaptively and distributes traffics in time and space domain. The effectiveness of the proposed method is evaluated through extended simulation experiments and basic hardware design.     

Study of information loss in packet voice systems

Once a voice buffer is full, it remains full for a certain period, during which many packets are possibly blocked, resulting in consecutive clippings in voice. The packet loss rate during this period changes slowly and has large fluctuations. It is shown that the temporal behavior of packet loss, especially at high rate, is inherently determined by voice correlation and system capacity and is independent of buffer size. Buffering may reduce the occurrence of short blocking periods associated with low rates packet loss but does not affect long ones associated with high packet loss rates. In fact, increasing the buffer size merely extends nonblocking periods, and thereby reduces the overall average packet loss rate, but packet-loss performance within existing blocking periods is not significantly improved. A simple tool is developed for calculating the boundary performance. It is found that it is possible to design a packet-switched voice system without buffering only at the expense of supporting a fewer number of calls. The issue of voice delay allocation between source and network is discussed, and it is shown that it is more effective to keep the network delay short while extending the source delay     

Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network

Banyan networks are being proposed for interconnecting memory and processor modules in multiprocessor systems as well as for packet switching in communication networks. This paper describes an analysis of the performance of a packet switch based on a single-buffered Banyan network. A model of a single-buffered Banyan network provides results on the throughput, delay, and internal blocking. Results of this model are combined with models of the buffer controller (finite and infinite buffers). It is shown that for balanced loads, the switching delay is low for loads below maximum throughput (about 45 percent per input link) and the blocking at the input buffer controller is low for reasonable buffer sizes.     

The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching

A new, high-performance packet-switching architecture, called the Knockout Switch, is proposed. The Knockout Switch uses a fully interconnected switch fabric topology (i.e., each input has a direct path to every output) so that no switch blocking occurs where packets destined for one output interfere with (i.e., block or delay) packets going to different Outputs. It is only at each output of the switch that one encounters the unavoidable congestion caused by multiple packets simultaneously arriving on different inputs all destined for the same output. Taking advantage of the inevitability of lost packets in a packet-switching network, the Knockout Switch uses a novel concentrator design at each output to reduce the number of separate buffers needed to receive simultaneously arriving packets. Following the concentrator, a shared buffer architecture provides complete sharing of all buffer memory at each output and ensures that all packets are placed on the output line on a first-in first-out basis. The Knockout Switch architecture has low latency, and is self-routing and nonblocking. Moreover, its Simple interconnection topology allows for easy modular growth along with minimal disruption and easy repair for any fault. Possible applications include interconnects for multiprocessing systems, high-speed local and metropolitan area networks, and local or toll switches for integrated traffic loads.     

On the analysis of burst-assembly delay in OBS networks and applications in delay-based service differentiation

In Optical Burst Switching (OBS), packets travel through the network core as part of longer-size optical bursts, which do not suffer electronic conversion until they reach an eggress point. Typically, such optical bursts comprise tens or hundreds of packets, which are assembled/deassembled at border nodes. During the burst-formation process, each arriving packet must wait until the final burst is complete, which clearly adds an extra delay on each packet in the burst, especially on those arriving earlier. However, such burst-assembly delay may be excessive for the appropriate performance of certain applications, mainly real-time interactive ones. This work’s findings are twofold: first, it characterises the burst-assembly delay distribution of each packet in a burst arisen by the main assembly algorithms found in the literature; and, second, it introduces a new burst-assembly strategy that takes into account the particular delay constrains of packets in the formation of optical bursts, along with a detailed study of its properties. This work has been funded by the “Ministerio de Educación y Ciencia” of Spain under grant TEC2006-03246.