High-frequency silicon alloy transistor

The silicon alloy transistor is a high-frequency, p-n-p type transistor capable of operation at high temperatures. Its temperature characteristic, derived principally from the use of silicon as the semiconductor, permits operation from - 70°C to 150°C. It achieves its high-frequency characteristic through accurate control of the base geometry. The n-type base of silicon is accurately machined by jet electrochemical techniques. Alloy contacts of aluminum are fused into the bottoms of the etch pits without producing appreciable change in base geometry. The depth of alloy is limited by the thickness of the aluminum, by the temperature, and by the length of time for alloying. Lead wires are soldered to the aluminum contacts and the transistor hermetically sealed in glass-metal containers. The electrical characteristics of typical silicon alloy transistors include an Icoof 0.005 µa, a common emitter forward current gain of 12, and an alpha-cutoff frequency of 12 mc.     

An alloy-diffuse silicon high current transistor with fast-switching possibilities

A method is described for the fabrication of a high-power silicon transistor capable of operating at case temperatures exceeding 100°C. Large-area transistors can be produced having uniform base widths of a few ten-thousandths of an inch. The base is established by the diffusion of impurities from a double-doped alloyed contact on the surface of the silicon. This device gives a common emitter current gain of greater than 30 at 10 amperes collector current and can dissipate 100 watts if the case temperature is held below 55°C. In addition it has constant common emitter current gain out to 200 kc, Hence this technique produces a power device combining both good current gain and frequency characteristics.     

Analysis of CMOS transistor instabilities

A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.     

High-frequency high-power static induction transistor

The principal operating mechanism of the static induction transistor (SIT) that shows exponential rather than the saturatedI-Vcharacteristics, is based on the static induction of both gate and drain voltages. It is known that the SIT has low noise, low distortion, and high audio-frequency power capability. The SIT is also a very promising device for high-frequency and high-power operation because of its short channel length, low gate series resistance, small gate-source capacitance, and small thermal resistance. Si SIT's which generate a 40-W output power at 200 MHz and 10 W at 1 GHz, with a cutoff frequency higher than 2.5 GHz, have been fabricated. This is the first step toward the realization of a power microwave SIT. Future developments of a higher power higher frequency SIT can be realized by employing a distributed electrode structure and traveling-wave operation.     

Reverse current instabilities in amorphous silicon Schottky diodes:modeling and experiments

A new model for high bias transport is reported which describes the time-dependent reverse current variations in amorphous silicon Schottky diodes. This phenomenon is of practical importance in the design and optimization of pixels for large-area optical and X-ray imaging. In the model, the main components of the reverse current, namely thermionic emission and tunneling, are both affected by the electric field at the metal/amorphous silicon interface. Time-dependent variations in this electric field arise due to the release of charges trapped in defect states in the depletion region and to charge trapping at the interface. This effect is analyzed using the approximation that the tunneling component of the current is equivalent to a lowering of the potential barrier at the interface. The calculated time-dependent reverse current is compared with the measured data     

Transport equations in heavily doped silicon,and the current gain of a bipolar transistor

The Fermi level and effective density of states are calculated for heavily doped silicon, using methods similar to those of Kleppinger and Lindholm and Van Overstraeten et al. For the case in which Boltzmann statistics can be applied to both types of carriers, modified transport equations are obtained in terms of two “heavy doping parameters,” which measure the magnitude and skewness of the effective forbidden band.These results are applied to the calculation of the d.c. current gain of a diffused bipolar transistor. We obtain reasonable current gain values without employing short carrier lifetimes, and our numerically calculated dependence of the current gain on injection level is reasonable. However, the quantitative accuracy of our calculations is limited by several factors.     

High-frequency performance of diamond field-effect transistor

The microwave performance of a diamond metal-semiconductor field-effect transistor (MESFET) is reported for the first time. MESFETs with a gate length of 2-3 μm and a source-gate spacing of 0.1 μm were fabricated on the hydrogen-terminated surface of an undoped diamond film grown by microwave plasma chemical vapor deposition (CVD) utilizing a self-aligned gate fabrication process. A maximum transconductance of 70 mS/mm was obtained on a 2 μm gate MESFET at V_GS=-1.5 V and V_DS=-5 V,for which a cutoff frequency f_T and a maximum oscillating frequency f_max of 2.2 GHz and 7 GHz were obtained, respectively     

High-frequency transistor modeling for circuit design

It has been found that certain high-frequency transistor types cannot be modeled accurately over wide frequency ranges with the hybrid pi or high-frequency T models even though reasonable extrinsic elements are added. Modifying the hybrid pi by replacing r/SUB /spl pi//C/SUB /spl pi// with an RC ladder extends the useful frequency range for that model to f/SUB T//2. A computer optimization program is used to determine the appropriate element values for the extended hybrid-pi model. For the 2N918, a two-section ladder gives a 3 : 1 improvement in the usable frequency range of the model.     

High-frequency transistor modeling for circuit simulation

The typical S parameters for the HP35826E microwave transistor have been used to derive a transistor model which is suitable for use in circuit analysis programs. The RMS difference between the S parameters of the model and the transistor data is 0.33 dB and 3.3/spl deg/ for frequencies between 0.1 and 8 GHz and DC collector currents between 5 and 20 mA. It is shown that the inclusion of time delays at the collector and base of the transistor model greatly improves the accuracy of the transistor model. With the inclusion of the time delays in the transisting model, a one-section R-C ladder network can be used to model the behavior of the base-emitter junction up to frequencies of the order of 2f/SUB T/.     

Current-voltage characteristics of a silicon nanowire transistor

The nanowires and nanotubes are being considered as the best candidates for high-speed applications. It is shown that the high mobility does not always lead to higher carrier velocity. The ultimate drift velocity due to the high-electric-field streaming are based on the asymmetrical distribution function that converts randomness in zero-field to streamlined one in a very high electric field. The limited drift velocity is found to be appropriate thermal velocity for a nondegenerately doped sample of silicon, increasing with the temperature, but independent of carrier concentration. However, the limited drift velocity is the Fermi velocity for a degenerately doped silicon nanowire, increasing with carrier concentration but independent of temperature. The results obtained are applied to the modeling of the current-voltage characteristics of a nanowire transistor.     

High-frequency transistor frequency multipliers and power amplifiers

A design theory for transistor frequency multipliers and power amplifiers is presented. The analytical approach is dependent upon two main assumptions, 1) that intrinsic base region behavior may be represented by a simple charge-control form model, and 2) that depletion layer charging current effects may be neglected initially and included when necessary as a perturbation of the analysis. The intrinsic base region is represented by a `partial sinusoid' model of base current flow during the conduction period of the emitter junction. This model is a simple representation of a complex process and is chosen on the basis of adequacy of characterization of the response of actual vices under practical operating conditions, together with a simple analytical form. The analysis of transistor frequency multiplier and power amplifier operation is developed in terms of the model and design relationships are presented. Results showing good agreement between the theory and measured data are given.     

High-frequency noise of the junction field-effect transistor

Based on Geurst's treatment of the high-frequency value of the admittances of the junction field-effect transistor, the high-frequency noise of the device has been computed, assuming that the noise source is of thermal origin. By applying an appropriate series expansion of the current it is possible to express the noise of the drain and gate current in terms of known quantities, as steady-state transconductance, gate capacitance, and frequency. At low frequencies the noise spectrum of the drain current is independent of the frequency and is much larger than the noise of the gate current; however, at high frequencies the noise spectra of the gate and drain current both vary by ω²and are of the same order of magnitude.     

High-frequency heterojunction bipolar transistor device design andtechnology

This paper identifies and reviews those aspects of new materials and device technological advances that have pushed HBT circuits towards a 100 GHz operating frequency. The operating principles of the HBT are initially discussed in relation to their differences from homojunction bipolar transistors. The advantages and disadvantages of the various materials systems available to HBTs, how the particular material properties relate to the device performance and a brief outline of growth technologies are then presented. Those device parameters contributing to the frequency performance figures-of-merit are identified and the resulting design approaches discussed. Current device fabrication technology is then reviewed, with the latest results and the most important design aspects for high-frequency operation identified. This is then followed by examples of achievements in both digital and analogue circuit applications. Finally, an attempt is made to identify those device and materials aspects that are likely to contribute to a further improvement in the frequency performance of HBTs     

Numerical solutions for a one-dimensional silicon n-p-n transistor

This paper describes a technique of obtaining numerical solutions of the basic carrier transport equations for a semiconductor and the results of some calculations pertaining to a silicon n-p-n transistor. The calculations include dc characteristics in direct and inverse operation, saturation parameters, and small-signal ac common emitterh-parameters. Both Boltzmann and Fermi statistics have been used, and the dependence of carrier mobilities on electric field has been taken into account.     

Microwave silicon Schottky-barrier field-effect transistor

Schottky-barrier field-effect transistors have been realised in silicon epitaxial films on high-resistivity silicon substrates. The 1 ?m wide gates are produced by projection-masking techniques. The maximum transconductances observed are 42 mA/V per mm gate length; the maximum frequency of oscillation fmax was 8 GHz.     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

A two-dimensional numerical analysis of a silicon N-P-N transistor

First-order transistor theory leads to conclusions that do not compare well with experimental results obtained for today's transistors fabricated with sophisticated technology. In an effort to overcome this situation, Gummel [1] for the first time used a digital computer to give a unified exact treatment of one-dimensional device performance. This paper treats the two-dimensional case that must be considered in order to account for lateral current effects. A set of 3 nonlinear partial differential equations describing the flow of carriers within the transistor under steady-state conditions is formulated and solved iteratively. The potential distribution and the hole and electron distribution within the transistor are calculated, and two-dimensional plots of these quantities are given.     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator