A New Method to Determine the Reliability Comparability for Products, Components, and Systems in Reliability Testing

A method is proposed in this paper to determine whether a product, a component, or a system in reliability life testing has a longer lifetime than the other. We propose two indices to compare reliability. The comparison is also distribution-free; i.e., it does not require the assumption on the lifetime distributions. A comparability index that is derived by integrating the weighted difference between the reliability functions of the two groups under comparison is named the "Better or Worse" (BOW) index. The second comparability index that is derived by calculating the overlapping area under the two distributions in comparison is named "Reliability Comparability" (RC) to quantify the degree of similarity between the two distributions. These two new indices are compared with the conventional methods currently used in the IC industries. Practical applications in lifetime-type reliability comparison are also illustrated in this paper     

Nanoscale silicon MOSFETs: A theoretical study

We have carried out extensive numerical modeling of double-gate, nanoscale silicon n-metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin, intrinsic channels connecting bulk, highly doped electrodes. Our model takes into account two most important factors limiting the device performance as the gate length is reduced, namely the gate field screening by source and drain, and quantum mechanical tunneling from source to drain. The results show that the devices with small but plausible values of gate oxide thickness t/sub ox/ and channel thickness t (both of the order of 2 nm) may retain high ON current, good saturation and acceptable subthreshold slope even if the gate length L is as small as /spl sim/5 nm, with voltage gain above unity all the way down to L/spl ap/2 nm (channel length L/sub c/=L+2t/sub ox//spl ap/5 nm). However, as soon as L is decreased below /spl sim/10 nm, specific power (per unit channel width) starts to grow rapidly. Even more importantly, threshold voltage becomes an extremely sensitive function of L,t, and t/sub ox/, creating serious problems for reproducible device fabrication.     

A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance $C_{rm of}$ dominates around 25% of the intrinsic gate capacitance $(C_{rm gint})$ in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor $C_{rm of}/C_{rm gint}$ above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.      

New Hot-Carrier Injection Mechanism at Source Side in Nanoscale Floating-Body MOSFETs

A new hot-carrier injection mechanism that depends on gate bias and body thickness in nanoscale floating-body MOSFETs has been identified using 2-D device simulation and hot-carrier degradation measurements. When gate voltage is sufficiently high and the body thickness is thin, the potential of the floating body is elevated due to the ohmic voltage drop at the source extension (SE), resulting in impact ionization at the SE. Hot-carrier stress with accelerated gate voltage may lead to a huge overestimation of lifetime in nanoscale floating-body MOSFETs.      

Experimental Method to Extract Effective Channel Length of Nanoscale n-MOSFETs

An experimental method of extracting the effective channel length L_eff from measured gate tunneling current (I_g) of nanoscale n-MOSFETs is proposed. The tunneling current from gate to the source and drain (I_gsd) was measured while applying a reverse bias to the substrate, and it was corrected for the depletion effect of the source/drain junctions. The gate tunneling current to the substrate (I_gc) was obtained by subtracting I_gsd from I_g. L_eff was calculated using a linear extrapolation of the I_gc versus gate length plot. The proposed method is a very simple and quite accurate method of extracting L_eff which does not require any additional assumptions and parameter extraction.     

DICE: A Beneficial Short-Channel Effect in Nanoscale Double-Gate MOSFETs

Physics-based compact modeling, supported by numerical simulations, is used to show the significance of "drain-induced charge enhancement" (DICE) in nanoscale double-gate (DG) MOSFETs. DICE, which is the strong-inversion counterpart of drain-induced barrier lowering (DIBL), is shown to significantly benefit drive current, without affecting the gate capacitance much, and hence can improve nanoscale DG CMOS speed substantially.     

A Quantum-Corrected Monte Carlo Study on Quasi-Ballistic Transport in Nanoscale MOSFETs

In this paper, the authors study a quasi-ballistic transport in nanoscale Si-MOSFETs based upon a quantum-corrected Monte Carlo device simulation to explore an ultimate device performance. It was found that, when a channel length becomes shorter than 30 nm, an average electron velocity at the source-end of the channel increases due to ballistic transport effects, and then, it approaches a ballistic limit in a sub-10-nm regime. Furthermore, the authors elucidated a physical mechanism creating an asymmetric momentum distribution function at the source-end of the channel and the influences of backscattering from the channel region. The authors also demonstrated that an electron injection velocity at a perfectly ballistic transport is independent of the channel length and corresponds well to a prediction from Natori's analytical model     

计算GaAs MESFET器件源电阻的新方法

采用一种直接估算微波 Ga As MESFET源电阻 Rs的方法。理论根据是反馈导纳的实部主要是由源电阻和栅电阻引起的 ,由此推导出 Rs相关的解析表达式。可在任何测量频率下采用解析方法计算出高精度的 Rs。把 Rg、Rd 与 Rs的比率以及 Ld、Lg 与 Ls 的比率作为优化参数 ,计算等效电路中的元件值相当快 ,且不依赖于初始值。等效电路与测量的 S参数拟合得相当好 ,而且计算出的元件都有物理意义     

A New Method to Determine the Failure Frequency of a Complex System

Two key indices in system reliability evaluation are the probability that the system is failed and the frequency of system failure. Other measures such as the mean cycle time and the mean down time can be easily derived from these quantities. This paper considers the reliability evaluation of a complex maintainable system using a cut set approach. The available literature on this subject generally deals with the failure probabilities. The technique proposed by Buzacott to determine the frequency of failure has the drawback that explicit formulae for system availability must be first derived. Numerical values are then obtained by further manipulation. This approach is, therefore, not suitable for computer application. The contribution of this paper is the development of a new formula for the frequency of system failure using a cut set approach, from which the numerical values can be obtained directly. This method overcomes the drawback of Buzacott's method and is suitable for computer application. Upper and lower bounds for frequency are also given and the method is illustrated by an example.     

Comparative Study of Energy Quantization Approaches in Nanoscale MOSFETs

An analytical model has been developed to study inversion layer quantization in the ultra thin oxide MOS(metal oxide semiconductor)structures using variation and triangular well approaches.Accurate modeling of the inversion charge density using the continuous surface potential equations has been done.No approximation has been taken to model the inversion layer quantization process.The results show that the variation approach describes inversion layer quantization process accurately as it matches well with the BSIM 5(Berkeley short channel insulated gate field effect transistor model 5)results more closely compared with triangular well approach.     

高阻衬底上具有n＋浮空层的横向Super Junction MOSFETs

提出了一种具有n^＋浮空层的横向superjunction结构，此结构通过磷或砷离子注入在高阻衬底上形成n^＋浮空层来消除传统横向superjunction结构中的衬底辅助耗尽效应．这种效应来源于P型的衬底辅助耗尽了superjunction区的n型层，使P与n之间的电荷不能平衡，n^＋层的REBULF效应通过使漏端电场减小，体电场重新分布而使新结构中的衬底承担了更多的电压，结果表明这种结构具有高的击穿电压、低的导通电阻和漂移区中电荷平衡的特点。     

一种求解LMS算法步长阀值的新方法

本文通过对失调方程的分析，提出由低次失调方程求解步长阀值的新方法，计算机模拟结果表明，采用本文方法计算步长是精确可行的。     

高阻衬底上具有n+浮空层的横向Super Junction MOSFETs

提出了一种具有n+浮空层的横向super junction结构,此结构通过磷或砷离子注入在高阻衬底上形成n+浮空层来消除传统横向super junction结构中的衬底辅助耗尽效应.这种效应来源于p型的衬底辅助耗尽了super junction区的n型层,使p与n之间的电荷不能平衡.n+层的REBULF效应通过使漏端电场减小,体电场重新分布而使新结构中的衬底承担了更多的电压.结果表明这种结构具有高的击穿电压、低的导通电阻和漂移区中电荷平衡的特点.     

一种高效的睫毛及眼睑检测方法

通过分析归一化虹膜图像中包含睫毛及眼睑的灰度特征,文中提出一种新的虹膜睫毛及眼睑检测方法,能够同时快速检测睫毛和眼睑,算法模型简单,复杂度低.首先对归一化虹膜图像进行中值滤波,然后用滤波后的图像与原图像做差,最后将做差的图像细化并去除伪目标点.通过对不同图库和一些特殊情况下采集到虹膜图像进行检测,证明该方法能够在很好检测睫毛及眼睑的同时,具有检测速度快,检测精度高的优点,克服了传统方法针对睫毛及眼睑建立不同的数学模型而导致复杂度增加,检测速度慢的缺点.     

一种有效去除测量噪声的新方法

本文利用信号与测量噪声在小波分析中不同尺度上的传播特性,研究了小波技术在涡流无损检测信号除噪中的应用.分析了传统的去除测量噪声的两种小波方法,Mallat多尺度边缘检测方法和阈值方法,针对两种方法的不足,作者提出了一种新方法,结果表明,此方法能有效地去除测量噪声.     

A Semiempirical Model to Determine HF Copper Losses in Magnetic Components With Nonlayered Coils

While in numerous power electronics applications, transformers and inductors with nonlayered windings are used, the absence up until now of any theoretical or even empirical model for their HF effective resistance calculation leads magnetic component designers to make high-error approximations. The typical approach until now has been to consider them as layered and apply some of the existent relevant models. The present paper establishes a new semiempirical model for the accurate determination of HF copper losses in windings with the random conductor distribution, a case that cannot be treated by any analytical method. This model is based on the statistical treatment of numerical results coming from a large number of simulations carried out with finite-element analysis software, and incorporates only three easily determinable parameters. The selected range for each of these parameters ensures that the model is suitable for the majority of practical applications. The theoretical analysis is verified by experimental measurements on different forms of winding geometries. A detailed investigation of the new formula reveals its inherent advantages on copper loss calculation when designing nonlayered coils.      

A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

Interface trap densities at gate oxide/silicon substrate (SiO₂/Si) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.     

High Thermoelectric Performance in PbTe Due to Large Nanoscale Ag2Te Precipitates and La Doping

Thermoelectrics are being rapidly developed for waste heat recovery applications, particularly in automobiles, to reduce carbon emissions. PbTe‐based materials with small (<20 nm) nanoscale features have been previously shown to have high thermoelectric figure‐of‐merit, zT, largely arising from low lattice thermal conductivity particularly at low temperatures. Separating the various phonon scattering mechanisms and the electronic contribution to the thermal conductivity is a serious challenge to understanding, and further optimizing, these nanocomposites. Here we show that relatively large nanometer‐scale (50–200 nm) Ag₂Te precipitates in PbTe can be controlled according to the equilibrium phase diagram and these materials show intrinsic semiconductor behavior with high electrical resistivity, enabling direct measurement of the phonon thermal conductivity. This study provides direct evidence that even large nanometer‐scale microstructures reduce thermal conductivity below that of a macro‐scale composite of saturated alloys with Kapitza‐type interfacial thermal resistance at the same overall composition. Carrier concentration control is achieved with lanthanum doping, enabling independent control of the electronic properties and microstructure. These materials exhibit lattice thermal conductivity which approaches the theoretical minimum above ～650 K, even lower than that found with small nanoparticles. Optimally La‐doped n‐type PbTe‐Ag₂Te nanocomposites exhibit zT > 1.5 at 775 K.     

A New Degradation Mechanism in High-Voltage SiC Power MOSFETs

The phenomenon of recombination-induced stacking faults in high-voltage p-n diodes in SiC has been previously shown to increase the forward voltage drop due to reduction of minority carrier lifetime. In this paper, it has been shown that, for the first time, this effect is equally important in unipolar devices such as high-voltage MOSFETs. If the internal body diode is allowed to be forward biased during the operation of these devices, then the recombination-induced SFs will reduce the majority carrier conduction current and increase the leakage current in blocking mode. The effect is more noticeable in high-voltage devices where the drift layer is thick and is not expected to impact 600-1200-V devices.