Technology of a new n-channel one-transistor EAROM cell called SIMOS

The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the floating gate. In the programming mode, electrons are accelerated by the channel drift field to energies high enough to overcome the barrier height of the Si-SiO2interface and so injected into the floating gate. On account of the channel-injection mechanism performed in the programming mode, channel lengths of less than 4 µm are required. A combination of this condition with the stacked-gate concept is achieved by a self-aligned technique which defines both polysilicon gates by a single photolithographic procedure. By means of the self-aligned technique, both the one-transistor EPROM cell and the one-transistor EAROM cell can be realized. Basic structures of the two different type one-transistor memory cells are the SIMOS transistor and the SIMOS tetrode, respectively. The technology of these two different SIMOS devices is described in detail and experimental results concerning charge accumulation, charge removal, and charge retention are reported.     

Polyoxide thinning limitation and superior ONO interpoly dielectricfor nonvolatile memory devices

Results obtained from a study on thin interpoly dielectrics, especially for nonvolatile memories with stacked-gate structures, are presented. First, the key factors which dominate the leakage current in polyoxide are reviewed, and intrinsic limitations in thinner polyoxide for device applications are investigated considering defect densities and edge leakage current. Second, the ONO (oxide/nitride/oxide) structure which overcomes polyoxide-thinning limitations is described. This stacked film reveals superior electric-field strength due to the inherent electron-trapping-assisted process. UV erase characteristics for EPROM cells with ONO structure are discussed. The slower erasing speed for EPROM cells with ONO interpoly dielectric is due to the decrease in photocurrent flow from a floating gate to a control gate     

GaAs m.a.o.s.f.e.t. memory transistor

A new non-volatile memory device is reported. This device is a GaAs m.o.s.f.e.t. with charge storage in the gate in which is a double oxide structure of aluminium oxide and GaAs native oxide, both oxides are grown anodically. The fabrication of the device is described and the results of initial measurements on the charging and charge retention properties are presented.     

A two-transistor SIMOS EAROM cell

A new, electrically alterable, nonvolatile memory cell, consisting of a floating gate memory transistor and an access transistor, has been developed using the self-aligned n-channel stacked-gate injection-type MOS (SIMOS) technique. Programming is achieved by two mechanisms: channel injection of hot electrons and field emission. Analysis of experimental data shows that the contribution of the field emission mechanism to programming is significantly high when the memory device operates in the depletion mode. Erase occurs via field emission of electrons from the floating gate through a thin oxide thermally grown on monosilicon to an n/SUP +/-diffusion area placed outside the channel region of the memory transistor. This additional floating gate/n/SUP +/-diffusion overlap is also utilized to increase the programming efficiency by applying a voltage to the n/SUP +/-diffusion terminal in addition to the gate and the drain voltage. This voltage is shown to have a strong influence on the two programming mechanisms. Memory retention compares favorably with that of the most advanced electrically programmable, read-only memory (EPROM) devices. Endurance is limited by charge trapping in the thin erase oxide to approximately 10000 write/erase cycles.     

A new method for the fast determination of the data retention lifetime of UV EPROM’s

The newly developped method involves a controlled partial erasure of a charged ultraviolet erasable programmable read only memory device followed by a period of high temperature storage. The model is based on two assumptions: the amount of charge stored at the floating gate of a programmed cell is assumed to be equal throughout a component and the trip the minimum level of charge stored at the floating gate of a programmed cell, has a Gaussian distribution throughout a component. The experimental data are well described by the model. After implementation of the experimental results in the model we extrapolate the data retention lifetimes of the UVEPROM’S under operational conditions. Our measurements show that most of the tested UVEPROM devices (64 ko to 256 ko) have a similar operational lifetime, only the charge leakage activation energy differs (0.35 to 0.9 eV) depending on the type of component. In conclusion this method and model are suitable for a fast determination of UVEPROM’S data retention lifetimes under operational conditions.     

A novel MONOS nonvolatile memory device ensuring 10-year dataretention after 107 erase/write cycles

A highly reliable nonvolatile memory device suitable for high-density electrically erasable and programmable read only memories (EEPROMs) is described. A metal-oxide-nitride-oxide-semiconductor (MONOS) structure whose top oxide is fabricated by chemical vapor deposition (CVD) on the nitride is proposed. This CVD oxide is densified by pyrogenic annealing and has stoichiometric SiO₂ characteristics. Its potential barrier, which prevents stored charges from decaying through the top oxide to the gate, thus becomes sharper than that of the thermally grown top oxide used in the conventional MONOS structure. For comparison between the proposed MONOS, conventional MONOS, and MNOS structures, three devices were fabricated on the same process line. The 16.7-nm nitride thickness in combination with a top oxide thickness of 4.0 nm results in a gate capacitance equivalent to that of the conventional NMOS structure with a 23.5-nm nitride thickness. Moreover, an asymmetric erase/write programming voltage has been adapted to the MONOS device operation by considering both erased-state degradation and written-state retention. At 85 °C, the proposed MONOS device has 10⁷-cycle endurance with 10-year data retention     

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications     

A new approach to simulating n-MOSFET gate current degradation byincluding hot-electron induced oxide damage

A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N_it ) and oxide trapped charge (Q_ox) were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N_it and Q_ox has thus been proposed. Furthermore, the individual contributions of N_it and Q_ox to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I_G,max. Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and flash EEPROM devices     

A source-side injection erasable programmable read-only-memory (SI-EPROM) device

A new erasable programmable read-only memory (EPROM) device with promise for low-voltage high-speed programming is described. This device is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control channel region introduced close to the source. At high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region also aids the injection of hot electrons into the floating gate. As a result, the source-side injection EPROM (SI-EPROM) has shown 10-µs programming speed at a drain voltage of 5 V.     

Buried injector logic, a vertical IIL using deep ion implantation

A vertically integrated alternative for integrated injection logic has been realized, named buried injector logic (BIL). 1 MeV ion implantations are used to create buried layers. The vertical pnp and npn transistors have thin base regions and exhibit a limited charge accumulation if a gate is saturated. d.c. and dynamic analysis of BIL-gate behaviour are given. A minimum gate delay of well below 1 ns is projected if collector areas are smaller than 10 μm² within an oxide isolated structure. A relation between maximum injector current density and device size is derived.     

Simulation of EPROM programming characteristics

An efficient method for the simulation of EPROM programming based on hydrodynamic calculations of electron energy within the device, is described. After the nonMaxwellian energy distribution is calculated, an expression for injected gate current is integrated to find the total gate charge and hence the threshold voltage shift, as a function of time. Comparison of theoretical and experimental results for actual EPROM programming validates this method.<>     

Lateral profiling of interface traps and oxide charge in MOSFETdevices: charge pumping versus DCIV

An improved oxide-charge and interface-trap lateral profiling charge pumping technique (iLPCP) is described. Erase-induced oxide charge and interface traps are investigated in flash EPROM devices. It is shown that the improved technique allows the extraction of profiles in cases where the previous method does not yield satisfactory results. A comparative study of iLPCP and of an existing direct current (DCIV) technique for lateral profiling of interface traps is conducted: both erase- and program-induced interface traps are investigated in flash EPROM devices. The results indicate that 1) iLPCP probes a much bigger portion of the gate region; 2) iLPCP probes a wider energy range; 3) DCIV is more sensitive deep in the channel and thus complements iLPCP     

A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices

A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices has been observed. This phenomenon is well characterized experimentally by studying devices with different gate oxide thickness, spacer width, and n-region doping. A good physical understanding is obtained by using a two-dimensional device simulation program together with experimental data analysis. This effect can be maximized for use as a potential low-voltage EPROM or avoided for reliability reason by properly designing the n-region doping, gate overlap, and oxide spacer width.     

Effects of erase source bias on Flash EPROM device reliability

This paper is concerned with the effects of the source bias during the erase operation on the reliability of Flash EPROM devices. It will be shown that positive charge in the tunnel oxide, mostly generated by the erase operation, is a major cause of the unintentional charge loss/gain mechanisms that disturb the data content of the memory cell. The effects of the erase source bias are evaluated in the context of the positive oxide charge generation and the resulting enhancement of the gate current that causes the data loss. An optimal source bias during erase, around 2 V for our samples, is shown to cause the least positive oxide charge. A model based on the band-to-band tunneling-induced hole generation in Si and subsequent hole injection during the erase operation is presented and discussed     

A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI DG-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly.     

A self-aligned EPROM structure with superior data retention

A structure that exhibits superior data retention, compared to the conventional erasable programmable read-only memory (EPROM) cell, while still using phosphosilicate glass (PSG) passivation, is described. The nitrided self-aligned MOS (NIT-SAMOS) employs a thin layer of low-pressure chemical vapor deposition (LPCVD) nitride between the double-poly-gate structure and the poly-metal isolation dielectric, to reduce the possibility of contamination of the floating-gate area. Comparisons are made of EPROM data retention lifetimes, programmability, and UV erasability, and n- and p-channel device parameters     

Damage-Less Sputter Depositions by Plasma Charge Trap for Metal Gate Technologies

Damage-free sputter deposition process has been developed for metal gate complementary metal-oxide-semiconductor technology. A plasma charge trap (PCT) was introduced in order to eliminate high-energy particle bombardment during sputter deposition processes. Molybdenum (Mo)-gated PMOSFETs were fabricated using a conventional gate-first process. It is shown that the PCT technology yields excellent characteristics in current drivability, as well as in gate oxide integrity (GOI) such as gate leakage current and charge-to-breakdown$(Q_BD)$. The metal gate was also applied to a nonvolatile memory (NVM), which would require most stringent damage control, and good retention characteristics were demonstrated.     

Famos—A new semiconductor charge storage device

A new non-volatile charge storage device is described. The floating gate avalanche injection MOS (FAMOS) structure is a p-channel silicon gate field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p-n junction to yield reproducible charging characteristics with long term storage retention.     

Determination of trapped oxide charge in flash EPROMs and MOSFETswith thin oxides

A technique for determining the sign and the effective density of the trapped oxide charge near the junction transition region, based on the measurement of the gate-induced drain leakage (GIDL) current, is used to investigate the hot-carrier effects resulting from the erase operation and bit-line stress in flash EPROM devices. While the trapped oxide charge depends on the stress conditions, it has been found that a significant amount of hole trapping is likely when a sufficiently large potential difference exists between the gate and junction for either an abrupt or graded junction