Ultra high temperature rapid thermal annealing of GaN

All of the major acceptor (Mg, C, Be) and donor (Si, S, Se and Te) dopants have been implanted into GaN films grown on Al₂O₃ substrates. Annealing was performed at 1100–1500°C, using AlN encapsulation. Activation percentages of ≥90% were obtained for Si⁺ implantation annealed at 1400°C, while higher temperatures led to a decrease in both carrier concentration and electron mobility. No measurable redistribution of any of the implanted dopants was observed at 1450°C.     

Gettering by heat thermal processing: application in crystalline silicon solar cells

The aim of this work is to getter unwanted impurities from solar grade crystalline silicon (Si) wafers and then to enhance their electronic properties. This was done by forming a sacrificial porous silicon (PS) layer on both sides of the Si wafers and by performing infrared (IR) thermal annealing treatments (at around 950 °C) in a SiCl₄/N₂ controlled atmosphere. The process allows concentrating unwanted impurities in the PS layer and near the PS/silicon interface. These treatments reduce the resistivity by about two orders of magnitude at a depth of about 40 μm and improve the minority carrier diffusion length from 75 to 210 μm. This gettering method was also tested on silicon wafers where grooved fingers and back contacts were achieved using a chemical vapor etching (CVE) method. Front buried metallic contacts and small holes for local back surface field were then achieved after the gettering stage in order to realize silicon solar cells. It was shown that the photovoltaic parameters of gettered silicon solar cells were improved as regard to ungettered ones.     

Dielectric reliability of stacked Al2O3–HfO2 MIS capacitors with cylinder type for improving DRAM data retention characteristics

Dielectric reliability in Al₂O₃(2–3.1nm)–HfO₂(3nm) stack capacitor with Metal–Insulator–Si(MIS) structure is investigated in this paper. We propose an optimized capacitor process through the Time–Dependent Dielectric Breakdown (TDDB) data under various process conditions. Furthermore, due to asymmetric current at both negative and positive voltage stress polarities, we show different lifetime extrapolation by a fluence–driven model. As a result, the maximum allowed operating voltage is projected to be 1.7V (failure rate 10ppm during 10year @ 85°C) for Data “0” retention lifetime.     

Magnetic nanostructures and nanodevices with a semiconductor or dielectric spacer

Magnetic properties of nanoscale magnetic-layer systems using FeNi, Co, FeMn, Al₂O₃, and SiC layers are studied experimentally. The dependence of magnetic behavior on the system geometry and parameters is addressed. Ferromagnet-semiconductor exchange coupling subject to the amplitude of an applied magnetic field is revealed. It is found that the magnetic behavior of the nanostructures varies in a nonlinear manner with applied magnetic field. Spin-tunneling magnetoresistance is observed in magnetic-layer junctions containing an Al₂O₃ spacer. In-plane-conduction magnetic-field sensors using an Al₂O₃ or a SiC spacer are fabricated and tested.Translated from Mikroelektronika, Vol. 34, No. 1, 2005, pp. 56–64.Original Russian Text Copyright © 2005 by Kasatkin, Muravjev, Plotnikova, Pudonin, Azhaeva, Sergeeva, Khodzhaev.     

N-channel thin-film transistors constructed on plastic by solution processes of HgSe nanocrystals

We demonstrate bottom-gate thin-film transistors (TFTs) based on solution-processed HgSe nanocrystals (NCs) on plastic substrates. Solid films made of spin-coated HgSe NCs were heated at a temperature of 150 °C for 15 min to maximize the magnitude of their current, and these films were utilized as the channel layers of TFTs. A representative TFT with a bottom-gate Al₂O₃ layer operated as a depletion-mode one with an n-channel, exhibiting a field effect mobility of 3.9 cm²/Vs and an on/off current ratio of about 10². In addition, the electrical characteristics of the TFT on bent substrates are briefly described.     

Effect of nano Al2O3 additions on the microstructure, hardness and shear strength of eutectic Sn–9Zn solder on Au/Ni metallized Cu pads

Nano-sized, nonreacting, noncoarsening Al₂O₃ particles have been incorporated into eutectic Sn–Zn solder alloys to investigate the microstructure, hardness and shear strength on Au/Ni metallized Cu pads ball grid array substrate (BGA). In the plain Sn–Zn solder joint and solder joints containing Al₂O₃ nano-particles, a scallop-shaped AuZn₃ intermetallic compound layer was found at the interfaces. In the solder joints containing Al₂O₃ nano-particles, a fine acicular-shaped Zn-rich phase and Al₂O₃ nano-particles were found to be homogeneously distributed in the β-Sn matrix. The shear strengths and hardness of solder joints containing higher percentage of Al₂O₃ nano-particles exhibited consistently higher value than those of plain solder joint and solder joints containing lower percentage of Al₂O₃ nano-particles due to control the fine microstructure as well as homogeneous distribution of Al₂O₃ nano-particles acting as a second phase dispersion strengthening mechanism. The fracture surfaces of plain Sn–Zn solder joints exhibited a brittle fracture mode with smooth surfaces while Sn–Zn solder joints containing Al₂O₃ nano-particles showed a typical ductile failure with very rough dimpled surfaces.     

Material property, compatibility, and reliability issues in diamond-enhanced, GaAs-based plastic packages

The mechanical performance and reliability of various Al₂O₃ ceramics were evaluated with intended applications as insulator frames for radio frequency/microwave power packages. Considering variations in base-flange material properties (CuW, CuMoCu), base-flange thickness (0.040 in., 0.020 in.), assembly process material (AgCu, Cu) assembly process temperature (860°C, 1080°C), and Al₂O₃ insulator material (96%, 99%, 20% ZrO₂/Al₂O₃, ZTA), finite element analysis (FEA) spatially resolved the fabrication-induced stresses during the assembly of CuW/Al₂O₃ and CuMoCu/Al₂O₃ structures and showed the critical regions to be the frame corners at the metal base-flange/Al₂O₃ interface. Bend strengths (four-point) and Weibull distributions were determined for each Al₂O₃ material and coupled with the FEA-predicted stresses for the various package configurations and assembly processes, the failure probabilities (P_f ) for the various CuW/Al₂O₃ and CuMoCu/Al₂O₃ structures were calculated. The CuMoCu-based structures exhibited the greatest warp deformation (concave upward, +), and highest stress and failure probability for all Al₂O₃ insulator varieties. The CuW-based structures exhibited an order-of-magnitude lower warp deformation (concave downward, −), an order-of-magnitude lower stress in the Al₂O₃, and in excess of seven orders-of-magnitude lower failure probability than CuMoCu-based structures, for all Al₂O₃ insulator varieties. Confirmational experiments were conducted using AgCu and direct-bond copper (DBC) assembly processes for selected varieties of CuW/Al₂O₃ and CuMoCu/Al₂O₃ structures. Al₂O₃ failure sites were identified using radiographic, ultrasonic and optical techniques and were in good agreement with model predictions of suspect structures and failure location. The strength and reliability data were considered in conjunction with relative cost for the Al₂O₃ ceramics to select an optimum frame insulator for the application.     

Electrical characterisation and reliability of HfO2 and Al2O3–HfO2 MIM capacitors

Current leakage and breakdown of MIM capacitors using HfO₂ and Al₂O₃–HfO₂ stacked layers were studied. Conduction in devices based upon HfO₂ layers thinner than 8 nm is probably dominated by tunnelling. Al₂O₃–HfO₂ stacked layers provide a limited benefit only in term of breakdown field. Constant-voltage wear-out of samples using insulating layer thicker than 6 nm is dominated by a very fast increase of the leakage current. A two step mechanism involving the generation of a conduction path followed by a destructive thermal effect is proposed to explain breakdown mechanism.     

On the analytical description of ageing kinetics in ceramic manganite-based NTC thermistors

Experimental results on thermally induced degradation tests carried out at the relatively low ageing temperatures less than 200 °C in NTC ceramic thermistors based on mixed transition-metal manganites (Cu,Ni,Co,Mn)₃O₄ are discussed. It is first established that, despite of chemical composition and technological features of the investigated ceramics, the stretched-exponential relaxation function of DeBast–Gillard or Williams–Watts is the unique analytical expression describing kinetics of the observed degradation processes.     

Thin-film encapsulation of polymer-based bulk-heterojunction photovoltaic cells by atomic layer deposition

This study demonstrated thin-film encapsulation of bulk-heterojunction polymer photovoltaic cells, utilizing a process based on atomic layer deposition (ALD) that both prevented degradation caused by ambient gases and served as an annealing step that increased the initial efficiency of the cells. With the ALD temperature set at 140 °C and the total deposition time set at 1 h, the photovoltaic cells, based on blended poly-3-hexylthiophene (P3HT) and [6,6]-phenyl C₆₁ butyric acid methylester (PCBM), were optimally annealed during encapsulation, achieving a power conversion efficiency (PCE) of 3.66%. Encapsulating the cells with a 26 nm Al₂O₃/HfO₂ nanolaminated film overcoated with an epoxy resin protection layer enabled the cells to obtain an in-air degradation rate that was similar to cells that were stored in nominally O₂/H₂O-free atmosphere. The nanolaminated structure of the encapsulation film resolved the issue of hydrolysis-induced aging observed with Al₂O₃ films, owing to the hydrophobicity of the HfO₂ layers. Additionally, extended exposure of the ALD precursors during the ALD process significantly improved the coverage of the ALD films over the P3HT/PCBM active layer at the perimeter of the cells.     

The formation and growth of intermetallic compounds and shear strength at Sn–Zn solder/Au–Ni–Cu interfaces

The microstructures and shear strength of the interface between Sn–Zn lead-free solders and Au/Ni/Cu interface under thermal aging conditions was investigated. The intermetallic compounds (IMCs) at the interface between Sn–Zn solders and Au/Ni/Cu interface were analyzed by field emission scanning electron microscopy and transmission electron microscopy. The results showed the decrease in the shear strength of the interface with aging time and temperature. The solder ball with highly activated flux had about 8.2% increased shear strength than that with BGA/CSP flux. Imperfect wetting and many voids were observed in the fracture surface of the latter flux. The decreased shear strength was influenced by IMC growth and Zn grain coarsening. In the solder layer, Zn reacted with Au and then was transformed to the β-AuZn compound. Although AuZn grew first, three diffusion layers of γ-Ni₅Zn₂₁ compounds were formed after aging for 600 h at 150 °C. The layers divided by Ni₅Zn₂₁ (1), (2), and (3) were formed with the thickness of 0.7 μm, 4 μm, and 2 μm, respectively.     

a-SiC:H/SiO2 Laminated Polarization Splitter for the Wavelength Region Longer Than 1.3 μm Prepared by Plasma-Enhanced Chemical Vapor Deposition

A laminated polarization splitter for the wavelength region longer than 1.3 μm is fabricated for the first time. It is composed of a-SiC:H/SiO₂ alternative multilayers prepared by plasma-enhanced chemical vapor deposition. Splitting behavior is also verified experimentally. It has low absorption loss even for the wavelength region around λ = 1.3 μm because the band-gap energy of a-Sic is larger than that of a-Si. The measured splitting angle is 13.8°, which is 2.4 times larger than the 5.7° splitting angle of rutile. The absorption loss of the multilayer is reduced to 1 × 10^-3 dB/μm at λ = 1.3 μm. The magnitude of the residual stress is 9.45 × 10⁸ dyn/cm², which is about one-third of that prepared by the rf bias sputtering equipment which is used for another project of our group. The deposition rate of SiO₂, is increased to 135 nm/min, which is 27 times larger than that prepared by the sputtering equipment.     

Reliability of 100 nm silicon nitride capacitors in an InP HEMT MMIC process

A reliability study has been conducted on capacitors made with 100 nm of silicon nitride, in an InP HEMT MMIC fabrication process. Special wafers were fabricated, containing 1482 200 × 200 μm² capacitors each, and these were probed automatically. They were subject to ramped-voltage stress and the breakdown voltages recorded. On a typical wafer the vast majority of the breakdown voltages are between 50 and 90 V. In addition, IV curves were measured on a small number of specimens from 0 V up to breakdown. This was done in two regimes: above 25 V with a conventional setup, and below 25 V with an ultra-low-current measurement system. These were done at 25 and 175 °C above 25 V, and at 25 °C only below 25 V. The data were fitted well with a model for the conductivity, consisting of ohmic conduction at low voltages and Frenkel–Poole conduction at high voltages. Parameters of the fits included thermal activation energies, the voltage acceleration factor in the Frenkel–Poole model, and d_eff, the effective thickness of the dielectric at the thinnest point. Analysis invoked the time-dependent dielectric breakdown model, which provides the time to failure as a function of the d_eff, while d_eff can be found from the ramped-voltage measurements. From the 10 wafers that have been probed so far, the mean of the distribution of failure times (at 1.5 V, 40 °C) is above 5 × 10⁷ h, and the distribution becomes insignificant below 2 × 10⁶ h. Further, the probability of failure in 10 years at 1.5 V, 40 °C is much less than 1 in 14,600. This indicates that 100 nm silicon nitride capacitors in this technology have good reliability.     

Characterisation of the Al2O3 films deposited by ultrasonic spray pyrolysis and atomic layer deposition methods for passivation of 4H–SiC devices

Al₂O₃ films were deposited using atomic layer deposition (ALD) and ultrasonic spray pyrolysis (USP) methods on p- and n-type Si substrates, n-type 4H–SiC substrates and 4H–SiC diodes for passivation studies. UV exposure in N₂ atmosphere and 5% HF treatment were used as two separate surface preparation procedures prior to Al₂O₃ deposition. The films deposited with USP technique contain a large amount of fixed negative charge and are vulnerable to water incorporation into the material. The Al₂O₃ film prepared by ALD method shows much better uniformity and less negative charge. Decrease of the leakage current in the 4H–SiC diodes is observed after Al₂O₃ passivation using both methods.     

Microwave properties of epitaxial large-area Ca-doped YBa2Cu3O7−δ thin films on r-plane sapphire

Ca doping of YBa₂Cu₃O_7−δ (YBCO) is well known to enhance the critical current density in large-angle grain boundaries for example of bicrystals. However, up to now no data are available on microwave properties of epitaxial Ca-doped YBa₂Cu₃O_7−δ thin films on r-plane sapphire with CeO₂ buffer layer.Therefore, first results are presented for large-area pulsed laser deposition (PLD) grown Ca_xY_1−xBa₂Cu₃O_7−δ films on 3-in. diameter sapphire wafers. The PLD process is optimised for undoped YBCO thin films and shows high reproducibility for YBCO. The microwave surface resistance R_s at 8.5 GHz of Ca-doped YBCO (x=0.1) thin films shows clear reduction (up to 20%) with respect to that of YBCO for temperatures from about 20–50 K. In addition, microwave surface resistance R_s of Ca-doped YBCO is lower than that of YBCO even for enhanced microwave surface magnetic field up to about 20 mT for temperatures 20 and 40 K.     

Growth of epitaxial Pr2O3 layers on Si(1 1 1)

The growth of Pr₂O₃ layers on Si(1 1 1) has been studied by X-ray diffraction, Low-energy electron diffraction (LEED) and atomic force microscopy (AFM). Pr₂O₃ starts to grow as a 0.6-nm thick layer corresponding to one unit cell of the hexagonal phase (1 ML). The X-ray results indicate that layers thicker than 0.6 nm do not grow with the hexagonal phase. Growth takes place at a sample temperature of 500–550 °C. Annealing of the monolayer in UHV at a temperature above 700 °C leads to the formation of Pr₂O₃ and PrSi₂ islands. Silicide islands are found only at annealing in UHV and do not occur at annealing in oxygen atmosphere of 10⁻⁸ mbar. The LEED pattern after heating to 730 °C shows a (2×2) and (√3×√3) superstructure and after heating to 1000 °C a (1×5) superstructure occurs. The superstructures seen in the LEED pattern arise from silicide structures in the area between the islands. The silicide remains on the surface and cannot be removed with flashing to 1100 °C. Further deposition of Pr₂O₃ on the surface covered with silicide phases does not lead to growth of ordered layers.     

Electrical and interfacial characteristics of nanolaminate (Al2O3/ZrO2/Al2O3) gate stack on fully depleted SiGe-on-insulator

The structural and electrical characteristics of a novel nanolaminate Al₂O₃/ZrO₂/Al₂O₃ high-k gate stack together with the interfacial layer (IL) formed on SiGe-on-insulator (SGOI) substrate have been investigated. A clear layered Al₂O₃ (2.5 nm)/ZrO₂ (4.5 nm)/Al₂O₃ (2.5 nm) structure and an IL (2.5 nm) are observed by high-resolution transmission electron microscopy. X-ray photoelectron spectroscopy measurements indicate that the IL contains Al-silicate without Ge atom incorporation. A well-behaved C–V behavior with no hysteresis shows the absence of Ge pileup or Ge segregation at the gate stack/SiGe interface.     

Design of a flat field fiber with very small dispersion slope

We have given designs of a small dispersion fiber with large effective area and small dispersion slope. The fiber has flat modal field over the central part of the core, which provides large mode field diameter (8.3 μm at λ₀=1550 nm) leading to the relatively large effective area (A_eff=56.1 μm²) required to reduce nonlinear effects. The total dispersion of the proposed fiber is in the range of 2.7–3.4 ps/km/nm in the wavelength range of 1530 to 1610 nm, which covers the entire C- and L-bands of erbium doped fiber amplifiers. The dispersion slope at λ₀=1550 nm is 0.01 ps/km/nm², which is also very small.     

Vibrational spectroscopy characterization of low-dielectric constant SiOC:H films prepared by PECVD technique

Low-dielectric constant SiOC:H films were prepared by plasma enhanced chemical vapour deposition (PECVD) from trimethyl-silane (H–Si–(CH₃)₃) and ozone (O₃) gas mixture. The samples were preliminarily annealed at 400 °C in N₂ atmosphere and then in N₂+He plasma. Afterwards, they were treated in vacuum at some fixed temperatures in the range between 400 and 900 °C. Structural investigations of the annealed films were carried out by means of vibrational spectroscopy techniques. FT-IR spectrum of a preliminarily treated sample shows absorption bands due to stretching modes of structural groups like Si–CH₃ at 1270 cm⁻¹, Si–O–Si at 1034 cm⁻¹ and C–H_x in the region between 2800 and 3000 cm⁻¹. No significant spectral change was observed in the absorption spectra of samples annealed up to 600 °C, indicating that the preliminarily treated film retains a substantial structural stability up to this temperature. Above 600 °C, absorption spectra show a strong quenching of H-related peaks while the band due to Si–O–Si anti-symmetric stretching mode shifts towards higher energy, approaching the value observed for thermally grown SiO₂. Raman spectra of samples treated at temperatures T500 °C exhibit both D and G bands typical of sp²-hybridised carbon, due to the formation of C–C bonds within the film which is accompanying the release of hydrogen. The intensity of D and G bands becomes more pronounced in samples annealed at higher temperatures, thus suggesting a progressive precipitation of carbon within the oxide matrix.     

Silicon dioxide deposited by ECR-PECVD for low-temperature Si devices processing

Silicon dioxide films have been deposited at temperatures less than 270 °C in an electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O₂, SiH₄ and He. The physical characterization of the material was carried out through pinhole density analysis as a function of substrate temperature for different μ-wave power (E_w). Higher E_w at room deposition temperature (RT) shows low defects densities (<7 pinhole/mm²) ensuring low-temperatures process integration on large area. From FTIR analysis and Thermal Desorption Spectroscopy we also evaluated very low hydrogen content if compared to conventional rf-PECVD SiO₂ deposited at 350 °C. Electrical properties have been measured in MOS devices, depositing SiO₂ at RT. No significant charge injection up to fields 6–7 MV/cm and average breakdown electric field >10 MV/cm are observed from ramps I–V. Moreover, from high frequency and quasi-static C–V characteristics we studied interface quality as function of annealing time and annealing temperature in N₂. We found that even for low annealing temperature (200 °C) is possible to reduce considerably the interface state density down to 5 × 10¹¹ cm⁻² eV⁻¹. These results show that a complete low-temperatures process can be achieved for the integration of SiO₂ as gate insulator in polysilicon TFTs on plastic substrates.