体硅FinFET三维模拟

利用三维模拟软件Davinci对体硅FinFET器件进行了详细的模拟.模拟结果显示体硅Fin-FET器件能够有效的抑止短沟道效应,具有驱动电流大、散热好、成本低等优点.为了获得好的亚阚值特性,Fin的厚度要比较薄,同时Fin的高度不能太低,以保持足够的高度来抑止短沟道效应.沟道可以采用低掺杂或未掺杂设计,从而减少沟道内杂质对载流子的散射作用和杂质涨落效应对器件性能的影响.另外,为了获得合适的器件阈值电压,体硅FinFET器件应当采用功函数在中间带隙附近的材料做栅电极,同时采用适当的功函数调节方法来获得合适的阈值电压.     

基于二维半导体的模拟电路最新进展

摩尔定律驱动的器件持续微缩已经开始给硅基晶体管的模拟性能带来潜在问题,其中本征增益作为最重要的模拟指标会随着技术节点的缩小而降低.二维半导体因其平坦的界面、原子级厚度的几何结构,允许极好的栅静电控制,并且不受短通道效应的影响而引起了广泛的关注.这些优异的特性使二维半导体在提高模拟电路性能中表现出巨大的潜力.本文中,我们...     

IMEC报道在高k／金属栅方面的进展

在国际电子器件会议（正DM）上,比利时的肌EC公司报道了其在改进平面CMOS性能方面的进展,是在32nm工艺代采用铪基高k电介质和碳化钽（TaC）金属栅。栅电介质与金属栅之间使用薄的介电质盖帽获得了低的阈值电压Vt和导带与价带边低的有效功函数（WFs）。另外,对栅堆栈加工只使用激光退火导致极小的“可维持”栅长大幅减小并改善了对短沟道效应的控制。对鳍形FET（finFET）应用与此相同的加工,可望将它用于22nm工艺代。     

高介电常数栅极电介质材料的研究进展

随着半导体技术的飞速发展,作为硅基集成电路核心器件的MOSFET的特征尺寸正以摩尔定律的速度缩小.然而,当传统栅介质层SiO2的厚度减小到原子尺寸时,由于量子隧穿效应的影响,SiO2将失去介电性能,致使器件无法正常工作.因此,必须寻找新的高介电常数材料来替代它.目前,高介电常数材料是微电子行业最热门的研究课题之一.主要介绍了栅介质层厚度减小所带来的问题(即研究高介电常数材料的必要性)、新型栅电介质材料的性能要求,并简要介绍和评述了近期主要高介电常数栅介质材料的研究状况及其应用前景.     

板级跌落碰撞下无铅焊点的有限元分析

为了预测跌落碰撞下球栅阵列(BGA)封装中无铅焊点的失效,采用ABAQUS软件来模拟跌落碰撞过程中焊点的应力分布.首先建立圆形电路板(PCB)组件的有限元模型,接着用模态试验和有限元模拟相结合的方法确定有限元模型的边界条件和PCB的阻尼参数,然后运用ABAQUS有限元软件模拟PCB组件从三种高度下跌落碰撞过程中BGA封装中无铅焊点的拉应力分布.结果表明:封装最外圈四个拐角焊点的拉应力最大,最大拉应力出现在焊点靠近封装的一侧.由此预测最外圈拐角的焊点最易失效,焊点失效的位置在靠近封装一侧.     

基于二维半导体的模拟电路最新进展（英文）

摩尔定律驱动的器件持续微缩已经开始给硅基晶体管的模拟性能带来潜在问题,其中本征增益作为最重要的模拟指标会随着技术节点的缩小而降低。二维半导体因其平坦的界面、原子级厚度的几何结构,允许极好的栅静电控制,并且不受短通道效应的影响而引起了广泛的关注。这些优异的特性使二维半导体在提高模拟电路性能中表现出巨大的潜力。本文中,我们回顾了基于二维半导体的模拟电路的最新研究进展。文章首先介绍了衡量模拟电路性能的重要指标,然后重点介绍了基于二维半导体的单级放大器的实现、接触工程、和互补技术,并进一步讨论了基于二维晶体管的复杂电路,如电流镜、运算放大器、射频电路。最后我们讨论了基于二维晶体管的模拟电路的应用前景和面临的关键挑战。     

纳米 MOSFET/SOI器件新结构

重点介绍器件进入纳米尺度后出现的MOSFET／SOI器件的新结构，如超薄SOI器件、双栅MOSFET、FinFET和应变沟道等SOI器件，并对它们的性能进行了分析。     

低压压印制备硅点阵结构的工艺研究

高密度、图形规则的硅点阵结构由于其独特的光电性能具有广泛的应用前景.本文介绍了一种以低压压印结合反应离子刻蚀制备硅点阵的方法,即利用PDMS模板通过压印复制获得PMMA掩模结构,用反应离子刻蚀在硅片表面制得高度有序的硅纳米点阵结构.实验和有限元模拟结果表明,低压压印因为毛细作用下光刻胶在模板内的充分填充可以获得良好的图形复制精度和较小的残余胶厚度,因此适于大面积高密度光刻胶结构的均匀复制.     

L形复合材料层板热压工艺密实变形过程的数值模拟

基于 Biot 固结原理和达西定律 , 建立了二维树脂流动与纤维密实模型 , 采用有限元方法实现了 L 形层板热压成型过程树脂压力分布、 层板变形的预测。通过对 AS4 炭纤维/环氧 350126 等厚层板厚度变化的模拟结果与实验数据的对比分析 , 证明了数学模型和有限元程序的可靠性。以阳模成型 90° 铺层 S22玻璃纤维/环氧 648L 形层板为例 , 对工艺过程层板厚度变化进行了分析。模拟结果表明 : 剪切模量对拐角以及拐角与平板过渡区域的变形影响较大 ; 平板长度对拐角区域变形影响较明显 , 对平板区的变形影响较小。采用热压罐制备了 90° 铺层S22玻璃纤维/环氧 648阳模成型 L 形层板 , 实验数据表明 , 固化后层板呈现拐角区厚、 平板区薄的厚度不均现象 , 并且平板长度对拐角区厚度变化影响较显著 , 这与数值预测结果具有较好的一致性。     

复合材料Ⅴ型构件的固化变形预测及其工装型面设计

利用固化动力学模型对20 mm厚度和3mm厚度的ZT7H/5429碳纤维复合材料层合板进行了固化模拟,在固化过程中,20 mm厚度平板出现了温度峰值,中心温度与表面温度差不超过6℃,3mm平板温度分布均匀,温度历程与热压罐工艺温度基本一致.利用简化的温度场和等效热膨胀系数对609和90°拐角的Ⅴ型基准试件进行了固化变形模拟,并进行了Ⅴ型基准试件的固化试验.60°和90°拐角试件的固化回弹角的模拟值分别为1.58°和1.18°,试验测得的回弹角的平均值分别为1.59°和1.11°.对Ⅴ型复合材料蒙皮构件进行了固化变形模拟,并得到了补偿过的工装型面,在该工装上成型的试件与设计形状基本一致.     

Sensitivity of Multigate mosfets to Process Variations–-An Assessment Based on Analytical Solutions of 3-D Poisson's Equation

This paper investigates the sensitivity of multigate MOSFETs to process variations using analytical solutions of 3-D Poisson's equation verified with device simulation. FinFET and Tri- gate with both heavily doped and lightly doped channels have been examined regarding their immunity to process-induced variations and dopant number fluctuation. Our study indicates that lightly doped FinFET has the smallest threshold voltage (V_th) dispersion caused by process variations and dopant number fluctuation. For heavily doped devices, dopant number fluctuation may become the dominant factor in the determination of overall V_th variation. The V_th dispersion of Tri-gate may therefore be smaller than that of FinFET because of its better immunity to dopant number fluctuation.     

Quantum mechanical device modeling: FinFET having an isolated n+/p+ gate region strapped with poly-silicon

In this paper, we present our numerical study on FinFET having an isolated n+/p+ gate region strapped with metal and poly-silicon structure. Our theoretical work is based on 2-D quantum-mechanical simulator with a self-consistent solution of Poisson-Schr?dinger equation. Our numerical simulation revealed that the threshold voltage (VT) is controlled within -0.1 approximately +0.2 V with varying the doping concentration of the n+ and p+ polysilicon gate region from 1.0 x 10(17) to 1.0 x 10(18) cm(-3). We also confirmed that the better VT tolerance of the FinFET on the variation of the fin thickness can be expected over the conventional FinFET structure. For instance, the VT of the FinFET under this work exhibited 0.02 V tolerance with respect to the variation of the fin thickness change of 5 nm (from 30 to 35 nm) while the traditional FinFET demonstrates the tolerance of 0.12 V for the same variation of the fin thickness.     

Extremely scaled 3-dimensional multiple-gate technologies for terabit era

In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.     

A novel submicron-gap electrode fabrication technology using thermal oxidation

A novel and reproducible method to fabricate submicron-gap electrodes using thermal oxidation has been presented. In this method, oxidation process determines the gap distance. The micron-level silicon electrode gaps with different shapes were first generated on the silicon wafer by conventional photolithography followed by deep reactive ion etching process. Then thermal oxidation was conducted to realize the transition from silicon to silicon dioxide, i.e. reduce the gap width. Finally, the planar electrodes with sub-micron spacing were formed by metallization and photolithography. Scanning electron microscopy (SEM) was used to examine the electrode configuration and the electrical properties of as-prepared electrode pairs were also characterized. The results showed that using the method investigated in this work, Au electrodes with a submicron-sized gap could be easily fabricated, with good uniformity and reproducibility.     

Evaluation of three-dimensional effects in short deep beams using a rigid-body-spring-model

Three-dimensional (3-D) effects in short deep beams without stirrups that failed in shear were investigated experimentally and analytically. Two deep beams with a shear span to depth ratio (a/d) of 0.5 and with different beam widths were tested. The effect of beam width on load-carrying capacity, failure mode, crack pattern and 3-D behavior was investigated, and shape effect due to beam width was clarified. In addition, the beams were analyzed by the 3-D rigid-body-spring model (RBSM). RBSM is a discrete form of modeling that presents realistic behavior from cracking to failure, and 3-D RBSM is applicable to simulate 3-D behavior as well as the confinement effect of concrete. Analytical results in terms of load–displacement curves and crack pattern are compared with the experimental results. Three-dimensional deformations, strut widths and cross-sectional stress distribution are investigated analytically and compared with the experimental results to determine 3-D behavior in detail. The 3-D effects in short deep beams are clarified.     

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

Coupled Mechanical and 3-D Monte Carlo Simulation of Silicon Nanowire MOSFETs

In this paper we report on a general methodology to investigate nanowire MOSFETs based on the coupling of mechanical simulation with 3-D real-space Monte Carlo simulation. The Monte Carlo transport model accounts for both strain silicon and quantum mechanical effects. Mechanical strain effects are accounted for through an appropriate change of the anisotropic band structure computed with the empirical pseudopotential method. Quantum effects are instead included by means of a quantum mechanical correction of the potential coming from the self-consistent solution of the Schrodinger equation. This methodology has been then applied to the simulation of a test case silicon nanowire n-MOSFET. Impact of mechanical strain and quantum effects on the drive current is investigated. It is shown that only the inclusion of strain and quantum mechanical effects allows a good agreement with experimental data, demonstrating the validity of the proposed methodology for ultimate devices.     

Optimal design of integrally gated CNT field-emission devices using a genetic algorithm

A method to optimize the focusing quality of integrally gated CNT field-emission (FE) devices by combining field-emission modeling and a computational intelligence technique, genetic algorithm (GA), is proposed and demonstrated. In this work, the e-beam shape, as a characteristic parameter of electron-optical properties, is calculated by field-emission simulation modeling. Using a design tool that combines GA and physical modeling, a set of structural and electrical parameters for four FE device groups, including double-gate, triple-gate, quadruple-gate and quintuple-gate type, were optimized. The resultant FE devices exhibit satisfactory e-beam focusabilities and the extracted parameters with the best performance for each type of FE device were represented to be fabricated by a VLSI technique. The GA-based automatic design parameter extraction will significantly benefit the design of integrated electron-optical systems for versatile vacuum micro-?and nano-electronic applications.     

Quantum Simulation of Device Characteristics of Silicon Nanowire FETs

A quantum simulation of silicon nanowire field-effect transistors has been performed in the frame work of the effective mass theory, where the three-dimensional Poisson equation was solved self-consistently with the mode-space nonequilibrium Green's function equations in the ballistic transport regime. The dependence of the device performance on the gate length and width for three types of gate configuration has been studied, focusing on the contribution of the tunneling current to the total current. The effects of gate underlap and the corner rounding of silicon body on the device performance have been also investigated quantitatively, leading to the conclusions that the gate underlap is an important factor in improving the subthreshold characteristics of the device, but the corner rounding of silicon body is not a significant factor, especially for devices with silicon body width of a few nanometers