Memory effects in hybrid silicon-metallic nanoparticle-organic thin film structures

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on silicon substrates and using organic thin films as the dielectric layers. These insulating thin films were produced by different methods, including spin-coating (polymethylmethacrylate), thermal evaporation (pentacene) and Langmuir–Blodgett deposition (cadmium arachidate). Gold nanoparticles, deposited at room temperature by chemical self-assembly, were used as charge storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A maximum memory window of 2.5 V was achieved by scanning the applied voltage of an Al/pentacene/Au nanoparticle/SiO₂/p-Si structure between 9 and −9 V.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer

In this study, a novel metal–semiconductor gate enhancement-mode (E-mode) and a metal–insulator-metal–semiconductor (MIMS) gate depletion-mode (D-mode) AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) on a single GaAs substrate have been developed by using high dielectric constant praseodymium insulator layer. The epitaxial layers were design for an enhancement-mode pHEMT after gate recess process. To achieve E/D-mode pHEMTs on single GaAs wafer, traditional Pt/Ti/Au metals were deposited as Schottky contact for E-mode pHEMTs and Pr/Pr₂O₃/Ti/Au were deposited as MIMS-gate for D-mode pHEMTs. This AlGaAs/InGaAs E-mode pHEMTs exhibit a gate turn-on voltage (V_ON) of +1 V and a gate-to-drain breakdown voltage of ?5.6 V, and these values were +7 V and ?34 V for MIMS-gate D-mode pHEMTs, respectively. Therefore, this high-k insulator in D-mode pHEMT is beneficial for suppressing the gate leakage current. Comparing to previous E/D-mode pHEMT technology, this E-mode pHEMTs and MIMS-gate D-mode pHEMTs exhibit a highly potential for high uniformity GaAs logic circuit applications due to its single recess process.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

Frequency and voltage dependence of negative capacitance in Au/SiO2/n-GaAs structures

The frequency (f) and bias voltage (V) dependence of electrical and dielectric properties of Au/SiO₂/n-GaAs structures have been investigated in the frequency range of 10 kHz–3 MHz at room temperature by considering the presence of series resistance (R_s). The values of R_s, dielectric constant (ε′), dielectric loss (ε″) and dielectric loss tangent (tan δ) of these structures were obtained from capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements and these parameters were found to be strong functions of frequency and bias voltage. In the forward bias region, C–V plots show a negative capacitance (NC) behavior, hence ε′–V plots for each frequency value take negative values as well. Such negative values of C correspond to the maximum of the conductance (G/ω). The crosssection of the C–V plots appears as an abnormality when compared to the conventional behavior of ideal Schottky barrier diode (SBD), metal–insulator–semiconductor (MIS) and metal–oxide–semiconductor (MOS) structures. Such behavior of C and ε′ has been explained with the minority-carrier injection and relaxation theory. Experimental results show that the dielectric properties of these structures are quite sensitive to frequency and applied bias voltage especially at low frequencies because of continuous density distribution of interface states and their relaxation time.     

Interface states in polyfluorene-based metal–insulator–semiconductor devices

Hybrid metal–insulator–semiconductor structures based on ethyl-hexyl substituted polyfluorene (PF2/6) as the active polymer semiconductor were fabricated on a highly doped p-Si substrate with Al₂O₃ as the insulating oxide layer. We present detailed frequency-dependent capacitance–voltage (C–V) and conductance–voltage characteristics of the semiconductor/insulator interface. PF2/6 undergoes a transition to an ordered crystalline phase upon thermal cycling from its nematic-liquid crystalline phase, confirmed by our atomic force microscope images. Thermal cycling of the PF2/6 films significantly improves the quality of the (PF2/6)/Al₂O₃ interface, which is identified as a reduced hysteresis in the C–V curve and a decreased interface state density (D_it) from ∼3.9 × 10¹² eV⁻¹ cm⁻² to ∼3.3 × 10¹¹ eV⁻¹ cm⁻² at the flat-band voltage. Interface states give rise to energy levels that are confined to the polymer/insulator interface. A conductance loss peak, observed due to the capture and emission of carriers by the interface states, fits very well with a single time constant model from which the D_it values are inferred.     

Charge-trapping characteristics of BaTiO3 with and without nitridation for nonvolatile memory applications

The charge-trapping characteristics of BaTiO₃ with and without nitrogen incorporation were investigated based on Al/Al₂O₃/BaTiO₃/SiO₂/Si (MONOS) capacitors. The physical properties of the high-k films were analyzed by transmission electron microscopy and X-ray photoelectron spectroscopy. Compared with the MONOS capacitor with BaTiO₃ as charge-trapping layer, the one with nitrided BaTiO₃ showed higher program speed even at lower operating voltage (4.3 V at +8 V for 100 μs), better endurance property and smaller charge loss (charge loss of 10.6% after 10⁴ s at 85 °C), due to the nitrided BaTiO₃ film exhibiting higher charge-trapping efficiency caused by nitrogen incorporation and suppressed leakage induced by nitrogen passivation.     

Polymer nanocomposite dielectric based on P(VDF-TrFE)/PMMA/BaTiO3 for TIPs-pentacene OFETs

TIPs-pentacene OFETs were fabricated on a plastic substrate using polymer nanocomposite dielectric. The blend polymer P(VDF-TrFE)/PMMA (30 wt%) was used as polymer matrix and BaTiO₃ nanoparticles modified by 3-glycidoxypropyltrimethoxysilane (GPTMS) were dispersed as ceramic fillers. The effects of different loadings of BaTiO₃ on the surface morphology and electrical properties of dielectric films were investigated. The formulation of screen-printable dielectric ink of P(VDF-TrFE)/PMMA/BaTiO₃/Silica (SII) was achieved by adding fumed silica as the viscosity modifier. TIPs-pentacene OFETs using SII as the gate dielectric features a mobility of 0.01 cm²/V s, and having a threshold voltage of −6 V. This screen-printable dielectric ink is promising for low operating-voltage fully-printed OFETs.     

Influences of post-annealing temperature on the structural and electrical properties of mixed oxides (CuFeO2 and CuFe2O4) thin films prepared by spray pyrolysis technique

P-type mixed oxides (CuFeO₂ and CuFe₂O₄) transparent conducting thin films have been successfully deposited on p-type Si (111) substrates at 450 °C by spray pyrolysis deposition (SPD) and annealed at 800 °C for 2 h. The crystal structure, surface morphology and electrical property have been investigated. It is observed that the CuFeO₂ and CuFe₂O₄ thin films as deposited and annealed, have polycrystalline hexagonal structure and the crystallite size increases by annealing processes. The electrical property of the Ni/CuFeO₂/Si Metal–Semiconductor–Metal (MSM) photo detectors was investigated using the current–voltage (I–V) measurements. The barrier heights ϕ_Β of Ni/CuFeO₂/Ni MSM thin films of as deposited and annealed on Si substrates were calculated and its values are 0.478, 0.345 eV, respectively with an applied bias voltage of 3 V.     

The effects of surface states and series resistance on the performance of Au/SnO2/n-Si and Al/SnO2/p-Si (MIS) Schottky barrier diodes

We have fabricated two types of Schottky barrier(SBDs),Au/SnO₂/n-Si (MIS1) and Al/SnO₂/p-Si (MIS2), to investigate the surface (N_ss) and series resistance (R_s) effect on main electrical parameters such as zero-bias barrier height (Φ_Bo) and ideality factor (n) for these SBDs. The forward and reverse bias current–voltage (I–V) characteristics of them were measured at 200 and 295 K, and experimental results were compared with each other. At temperatures of 200 and 295 K, Φ_Bo, n, N_ss and R_s for MIS1 Schottky diodes (SDs) ranged from 0.393 to 0.585 eV, 5.70 to 4.75, 5.42×10¹³ to 4.27×10¹³ eV^?1 cm^?2 and 514 to 388 Ω, respectively, whereas for MIS2 they ranged from 0.377 to 0.556 eV, 3.58 to 2.1, 1.25×10¹⁴ to 3.30×10¹⁴ eV^?1 cm^?2 and 312 to 290 Ω, respectively. The values of n for two types of SBDs are rather than unity and this behavior has been attributed to the particular distribution of N_ss and interfacial insulator layer at the metal/semiconductor interface. In addition, the temperature dependence energy density distribution profiles of N_ss for both MIS1 and MIS2 SBDs were obtained from the forward bias I–V characteristics by taking into account the bias dependence of effective barrier height (Φ_e) and R_s. Experimental results show that both N_ss and R_s values should be taken into account in the forward bias I–V characteristics. It has been concluded that the p-type SBD (MIS2) shows a lower barrier height (BH), lower R_s, n and N_ss compared to n-type SBD (MIS1), which results in higher current at both 200 and 295 K.     

Device characteristics of AlGaN/GaN MIS–HEMTs with high-k HfxZr1−xO2 (x = 0.66, 0.47, 0.15) insulator layer

This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with Hf_xZr_1−xO₂ (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered Hf_xZr_1−xO₂ with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO₂, the V_TH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum I_DS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at V_GS = 3 V, respectively.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Pulse electrodeposited copper indium sulfide films

Copper indium sulfide (CISu) films were deposited by the pulse galvanostatic deposition technique at different duty cycles. The films are polycrystalline with peaks corresponding to the chalcopyrite phase of CISu. The grain size and surface roughness increased from 10 to 25 nm and 0.85 to 2.50 nm respectively with increase of duty cycle. Optical band gap in the range of 1.30–1.51 eV was observed for the films deposited at different duty cycles. Room temperature resistivity of the films is in the range of 0.1–3.67 Ω cm. Photoconductivity measurements were made at room temperature. Photocurrent spectra exhibited maximum corresponding to the band gap of copper indium sulphide. CdS/CuInS₂ fabricated with CISu films deposited at 50% duty cycle have exhibited a V_oc of 0.62 V, J_sc of 16.30 mA cm^?2, FF of 0.71 and efficiency of 7.16%.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

Controlling the electrical characteristics of Au/n-Si structures by interfacial insulator layer

Admittance (C–V and G/ω–V) measurements of Au/n-Si (metal–semiconductor, MS) and Au/SnO₂/n-Si (metal–insulator–semiconductor, MIS) structures were carried out between 1 kHz and 1 MHz at room temperature to investigate the interfacial insulator layer effect on the electrical characteristics of Au/n-Si structures. Experimental results showed that MIS structure's capacitance (C) values, unlike those of MS structure, became stable especially at high frequencies in the accumulation region. Also, the insulator layer caused structure's shunt resistance (R_sh) to increase. It was found that series resistance (R_s) is more effective in the accumulation region at high frequencies after the correction was applied to C and G/ω data to eliminate the R_s effect. The density of interface states (D_is) was obtained using Hill–Coleman method, D_is values MIS structure was obtained smaller than those of MS structure. Results indicate that interfacial insulator layer brings about some improvements in electrical characteristics of Au/n-Si structures.     

A study on MIS Schottky diode based hydrogen sensor using La2O3 as gate insulator

In this work, a Metal–Insulator–Semiconductor (MIS) based Schottky-diode hydrogen sensor was fabricated with La₂O₃ as a gate insulator. The electrical properties (current–voltage characteristics, change in barrier height and sensitivity) and hydrogen sensing performance (dynamic response and response time) were examined from 25 °C to 300 °C and towards H₂ with different concentrations. The conduction mechanisms were explained in terms of Fowler–Nordheim tunneling (below 120 °C) and the Poole–Frenkel effect at temperatures (above 120 °C). The results show that at an operating temperature of 260 °C, the sensitivity of the device can reach a maximum value of 4.6 with respect to 10,000-ppm hydrogen gas and its response time was 20 s.     

Electrical and photovoltaic properties of SnSe/Si heterojunction

Thin film of SnSe is deposited on n-Si single crystal to fabricate a p-SnSe/n-Si heterojunction photovoltaic cell. Electrical and photoelectrical properties have been studied by the current density–voltage (J–V) and capacitance–voltage (C–V) measurements at different temperatures. The fabricated cell exhibited rectifying characteristics with a rectification ratio of 131 at ±1 V. At low voltages (V<0.55 V), the dark forward current density is controlled by the multi-step tunneling mechanism. While at a relatively high voltage (V>0.55 V), a space charge-limited-conduction mechanism is observed with trap concentration of 2.3×10²¹ cm⁻³. The C–V measurements showed that the junction is of abrupt nature with built-in voltage of 0.62 V which decreases with temperature by a gradient of 2.83×10⁻³ V/K. The cell also exhibited strong photovoltaic characteristics with an open-circuit voltage of 425 mV, a short-circuit current density of 17.23 mA cm⁻² and a power conversion efficiency of 6.44%. These parameters have been estimated at room temperature and under light illumination provided by a halogen lamp with an input power density of 50 mW cm⁻².     

Model based precise analysis of the injection currents in Al/ZrO2/Al2O3/ZrO2/SiO2/Si structures for use in charge trapping non-volatile memory devices

Metal/insulator/Silicon (MIS) capacitors containing multilayered ZrO₂/Al₂O₃/ZrO₂/SiO₂ dielectric were investigated in order to evaluate the possibility of their application in charge trapping non-volatile memory devices. The ZrO₂/Al₂O₃/ZrO₂ stacks were deposited by reactive rf magnetron sputtering on 2.4 nm thick SiO₂ thermally grown on p-type Si substrate. C–V characteristics at room temperature and I–V characteristics recorded at temperatures ranging from 297 K to 393 K were analyzed by a comprehensive model previously developed. It has been found that Poole-Frenkel conduction in ZrO₂ layers occurs via traps energetically located at 0.86 eV and 1.39 eV below the bottom of the conduction band. These levels are identified as the first two oxygen vacancies related levels in ZrO₂, closest to its conduction band edge, whose theoretical values reported in literature are: 0.80 eV, for fourfold, and 1.23 eV, for threefold coordinated oxygen vacancies.     

Fabrication of CdSe sensitized SnO2 nanofiber quantum dot solar cells

In the present study, we report a cost-effective quantum dot solar cells based on a combination of electrospinning and successive-ionic-layer-adsorption and reaction (SILAR) methods. CdSe nanocrystals are deposited on electrospun SnO₂ nanofibers by SILAR method using CdCl₂ as the cadmium source and Na₂Se as selenium source. The as-prepared materials are characterized by spectroscopy and microscopy. CdSe deposited SnO₂ electrodes are also characterized by spectroscopy and microscopy. Cells are fabricated with platinum (Pt)-sputtered FTO glasses used as the counter electrodes and polysulfide solution used as the electrolyte. The efficiency of the cells is studied for different number of SILAR cycles. Current density–voltage (J–V) measurements on a cell having CdSe deposition of 7 SILAR cycles and SnO₂ coating area 0.25 cm² showed an overall power conversion efficiency of 0.29 % with a photocurrent density (J_SC) of 5.32 mA cm⁻² and open circuit voltage (V_OC) of 0.23 V under standard 1 Sun illumination of 100 mWcm⁻² (AM 1.5 G conditions). This is improved by carefully coating SnO₂ film without losing the structures. Also ZnS passivation layer is coated to obtain an improved efficiency of 0.48% with J_SC of 4.68 mAcm⁻², and V_OC of 0.43 V.     

Electrical properties and barrier modification of GaAs MIS Schottky device based on MEH-PPV organic interfacial layer

We report fabrication and electrical characterization of GaAs based metal-interfacial layer-semiconductor (MIS) device with poly[2-methoxy-5-(2^/-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), as an interfacial layer. MEH-PPV raises the barrier height in Al/MEH-PPV/p-GaAs MIS device as high as to 0.87 eV. A Capacitance-Voltage (C–V) characteristic exhibits a low hysteresis voltage with an interface states density of 1.69×10¹¹ cm⁻² eV⁻¹. Moreover, a high transition frequency (f_c) of about 50 kHz was observed in the accumulation mode. The photovoltaic response of Al/MEH-PPV/p-GaAs device was measured under the air masses (AM) 1.0 and 1.5. The open circuit voltage (V_OC), short circuit current (I_SC), fill factor and the efficiency of the Al/MEH-PPV/p-GaAs device were found to be 1.10 V, 0.52 mA, 0.65, and 5.92%, respectively, under AM 1.0 condition.