Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I_DS and different extremes temperatures ΔT values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO₂ interface.     

Performance drifts of N-MOSFETs under pulsed RF life test

This paper presents a reliability life test bench specifically dedicated to high RF power devices for lifetime tests under pulse conditions. The monitoring of RF power, drain, gate voltages and currents under various pulses and temperatures conditions are investigated. A 3000 h pulsed RF life test has been conducted on a dedicated RF S-band test bench in operating modes. The investigation findings of degradations of critical electrical parameters derived from the data treatment after this accelerated ageing tests are presented. Numerous duty cycles are applied in order to stress Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS). It shows with tracking of a set of RF parameters (P_out, Gain and Drain Efficiency: DE) that the dominant degradation phenomenon is linked to hot carriers generated interface states (traps) and trapped electrons. Which results in a build up of negative charge at Si/SiO₂ interface and the main cause appear with incidence on RF power device. Physical simulation software (Silvaco-Atlas) has been used to locate and confirm these phenomena.     

Effects of electromagnetic near-field stress on SiGe HBT’s reliability

In this paper, a reliability damage mechanism was presented in SiGe Heterojunction Bipolar Transistor (HBT). This new stress methodology differs from conventional SiGe, HBT device reliability associated with other stresses, since it was obtained by applying electromagnetic near-field aggression. The near-field set-up is used to disturb with electromagnetic field the Device Under test (DUT) on a localized area. Degradations in the base current and the current gain are identified. They are induced by a large base current leakage due to hot carrier which introduces generation/recombination trap centers at the silicon–oxide interface of the emitter–base spacer. By using the S-parameters measurements, we find that both forward transmission scattering parameter (S₂₁) and the input scattering parameter (S₁₁) are affected by this stress. In addition the power characteristics of DUT are also affected by stress. A Direct Power Injection (DPI) method is used to understand the near-field stress behaviour.     

Leakage current effects on N-MOSFETs after thermal ageing in pulsed life tests

This paper presents a synthesis of leakage current effects on N-MOSFET performances, after thermal ageing in pulsed life tests. A 3000 h pulsed RF life test has been conducted on a dedicated RF S-band bench in operating modes. It is interesting to understand the degradation mechanism effects caused by the increase leakage current and in turn on drifts of critical parameters. It shows with tracking of a set of RF parameters (Pout, Gain and Drain Efficiency: DE) that only Hot Carrier Injection (HCI) phenomenon appears with incidence on RF. It is the main cause for device degradation leading to the interface state generation (traps), which results in a build up of negative charge at Si/SiO₂ interface. The physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations to locate and confirm these phenomena.     

Hot electrons induced degradation in lattice-matched InAlN/GaN high electron mobility transistors

In this paper, lattice-matched Pt/Au-In_0.17Al_0.83N/GaN high electron mobility transistors (HEMTs) were fabricated, and the degradation characteristics of the gate leakage current were investigated by drain-to-source voltage (V_DS) step-stress measurements under the ON, semi-ON, and OFF stress conditions and at different temperatures, respectively. It is found that, (1) there exists a critical value of V_DS, beyond which the gate leakage current begins to increase significantly; and (2) the degradation of gate leakage current has a positive temperature coefficient, indicating that high temperature can accelerate the degradation. A hot electron model is used to explain the experimental results, emphasizing that the hot electrons from the channel can induce additional negatively charged defects at the InAlN/GaN interface, which can increase the local electrical field and introduce a thinner surface barrier and finally enhance the vertical leakage current component, leading to the current degradation.     

Reliability study of power RF LDMOS device under thermal stress

This paper presents the results of comparative reliability study of two accelerated ageing tests for thermal stress applied to power RF LDMOS: Thermal Shock Tests (TST, air-air test) and Thermal Cycling Tests (TCT, air-air test) under various conditions (with and without DC bias, TST cold and hot, different extremes temperatures ΔT). The investigation findings of electrical parameter degradations after various ageing tests are discussed. On-state resistance (R_{ds_on}) is reduced by 12% and feedback capacitance (C_rss) by 24%. This means that the tracking of these parameters enables to consider the hot carrier injection as dominant degradation phenomenon. To reach a better understanding of the physical mechanisms of parameter's shift after thermal stress, a numerical device model (2D, Silvaco-Atlas) was used to confirm degradation phenomena.     

Impact of Hf content on positive bias temperature instability reliability of HfSiON gate dielectrics

Metal-oxide-semiconductor field-effect transistors (MOSFETs) incorporating HfSiON dielectrics with different compositions have been fabricated using atomic layer deposition (ALD) and their positive bias temperature instability (PBTI) reliability has also been investigated. The experimental results indicate that the oxide trapped charge (N_ot) dominates the PBTI degradation process, and after PBTI stress the increment of oxide trapped charges (ΔN_ot) is about 2-3 orders of magnitude greater than the generation of interface traps (ΔN_it). Moreover, higher Hf concentration results in more pre-existing traps but slower trap creation rate. The charge pumping technique has been utilized to characterize the interfacial parameters, ΔN_it, ΔN_ot, and ΔD_it (the generation of the density of interface trap per energy and area).     

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

In the present work we study reliability issues of Pt/HfO₂/Dy₂O₃/n-Ge MOS structures under various stress conditions. The electrical characteristics of the micro-capacitors are very good probably due to the presence of a rare earth oxide as interfacial layer. It is shown that the injected charge (Q_inj) at high constant voltage stress (CVS) conditions induces stress-induced leakage current (SILC) that obeys a power-law. We also observe a correlation between the trapped oxide charge and SILC, which is, at low stress field, charge build-up and no SILC, while at high stress field SILC but few trapped charges. Results show that the present bilayer oxides combination can lead to Ge based MOS devices that show acceptable degradation of electrical properties of MOS structures and improved reliability characteristics.     

Difference between the 1/f noise spectral density before and after stress as a measure of the submicron MOS transistors degradation

The paper deals with the 1/f noise as a measure of the submicron MOS transistor degradation. As the reference point of the investigations has been assumed the plot of the 1/f noise drain voltage spectral density S_VD versus the channel length L of the long-channel device which in log-log scale is linear (1/L) at slope equals −1. A theoretical analysis and experimental investigations indicate that before stress decrease of the carrier effective mobility, when the MOS transistors channel becomes shorter, causes deviate down of the plot S_VD vs. L in comparison with the extrapolated linear plot of the long channel device. During stress the hot-electron effect leads to the out of controll generation of additional interface states near drain edge which influence on deviate up of the plot S_VD vs. L in comparison with the value before stress. The measure of the degradation due to the hot-electron effect is difference between S_VD after and before stress. It is showed that S_VD of the extrinsic transistors do not dependent on the parasitic resistances therefore the considerations concern both of the conventional and LDD-MOS devices. Moreover the fundamental conditions of the measurement have been determined     

Analytical Low Frequency NBTI Compact Modeling with H<Subscript>2</Subscript> Locking and Electron Fast Capture and Emission

Besides reaction-diffusion theory explaining the generation and passivation of interface trap (ΔN_IT), hole trapping/de-trapping in preexisting gate insulator traps and transient charge occupancy in ΔN_IT are also combined to describe the characteristic of NBTI degradation. However, it is found that H₂ locking effect and Electron Fast Capture/Emission play key roles in the NBTI degradation. In this paper, an analytical low frequency AC NBTI compact model has been proposed to accurately predict the shift in threshold voltage. Two fitting parameters (α and F_FAST) have been introduced to account for the H₂ locking and fast electron capture and emission. The comparison between the proposed model and the experimental data has been carried out, and the results show that our proposed can catch the kinetics of NBTI degradation under low frequency AC stress conditions.     

Behavior of substrate enhanced electron injection in advanced deep sub-micron NMOSFETs

Hot carrier degradation under conventional maximum substrate current I_b,max, electronic gate current I_g (HE) and substrate enhanced electron injection (SEEI) in advanced deep sub-micron NMOSFETs is studied. It is found that the interface trap generation is the dominant mechanism for hot carrier degradation under these three stress conditions. Furthermore, the behavior of SEEI under AC stress applied to the gate is investigated by charge pumping. The results indicate that the interface trap generation is also the dominant mechanism for hot carrier degradation under AC stress. However, due to the recovery of SEEI, the degradation of the electrical parameters for NMOSFETs at equally effective stress duration under AC stress is slightly less than that under DC stress. Finally, the recovery behavior of secondary impact ionization damage is discussed by using an on-the-fly technique and the charge pumping spot measurement technique. It is found that the passivation of the interface traps is directly responsible for the recovery of I_dlin.     

Accurate modeling of nanoscale gate underlap SOI MOSFET and design of low noise amplifier for RF applications

Paper presents an accurate model by accounting non-quasi-static and extrinsic parasitic effects for 90 nm gate underlap SOI MOSFETs for RF applications. Generated Y-parameters from the model up to 20 GHz matched very well with 2D ATLAS (with an average error of ～5%), whereas results from quasi-static predictive technology model differ significantly (>20%). Calculated transit frequency f _T and maximum frequency of oscillation f _max have been found as ～108 and ～130 GHz respectively. Simulated noise figure at drain-to-source current I _DS ≈ 0.64mA and drain-to-source voltage V _DS=1 V was found to be ≈2.8 dB with gate resistance R _ge = 3 Ω. A low noise amplifier (LNA) designed at operating frequency of 5.8 GHz using the model has shown good match at input (S ₁₁ ≈ ?15 dB), output (S ₂₂ ≈ ?16 dB) and gain (S ₂₁ ≈ 15 dB). A new figure-of-merit of LNA (FoM_LNA) involving signal power gain G, noise factor F and dc power consumption P _dc has been proposed. By comparing with limited available measured data of 180 nm bulk, it has been found that underlap LNA (simulated using the developed model) gives almost three times improvement in the proposed FoM_LNA.     

Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET

In this paper, the performance of asymmetric underlapped FinFETs (U-FinFETs) is analyzed for linearity and harmonic distortion at high temperatures. The harmonic distortion that arises as a result of non-linear device characteristics requires a detailed analysis for better RF reliability performance. The variations in linearity and distortion characteristics with temperature are analyzed with regards to the primary components of harmonic distortion, second order distortion (HD2), third order distortion (HD3), and the total harmonic distortion (THD). For detailed understanding of the distortion characteristics of U-FinFETs, different device parameters such as the drain current (I_ds) and transconductance (g_m) are also analyzed. The results of the analysis suggest that the U-FinFETs present a significant reduction in harmonic distortion at elevated temperatures under subthreshold regime and restrict the degradation in harmonic distortion in the superthreshold regime resulting in better reliability for RF applications.     

A 5000 h RF life test on 330 W RF-LDMOS transistors for radars applications

A reliability test bench dedicated to RF power devices is used to improve 330 W LDMOS in a radar conditions. The monitoring of RF power, drain, gate voltages and currents under various pulses and temperatures conditions are investigated. Numerous duty cycles are applied in order to stress LDMOS. It shows with tracking all this parameters that only few hot carrier injection phenomenon appear with no incidence on RF figures of merit (P_out or PAE). Robustness and ruggedness are shown for LDMOS with this bench for radar applications in L-band.     

Effect of Si capping layer on the interface quality and NBTI of high mobility channel Ge-on-Si pMOSFETs

The effects of a Si capping layer on the device characteristics and negative bias temperature instability (NBTI) reliability were investigated for Ge-on-Si pMOSFETs. A Ge pMOSFET with a Si cap shows a lower subthreshold slope (SS), higher transconductance (G_m) and enhanced drive current. In addition, lower threshold voltage shift and G_m,max degradation are observed during NBTI stress. The primary reason for these characteristics is attributed to the improved interface quality at the high-k dielectric/substrate interface. Charge pumping was used to verify the presence of lower density of states in Ge pMOSFETs with a Si cap.     

Stress induced degradation features of very thin gate oxides

The degradation features of very thin gate oxide after Fowler-Nordheim stress have been studied. Bulk oxide, cathodic and anodic regions have been analysed from the charge build-up point of view, as well as the stress induced generation of Si/SiO₂ fast interface state density. A physical interpretation of experimental results has been proposed, involving two types of stress induced positive charge building up at interface regions. It is shown that a critical oxide thickness exists, under which the degradation mechanisms could be considerably different.     

Hot carrier reliability of RF N- LDMOS for S Band radar application

This paper presents an innovative reliability bench specifically dedicated to high RF power device lifetime tests under pulse conditions for radar application. A base-station dedicated LDMOS transistor has been chosen for RF lifetests and a complete device electric characterization has been performed. A whole review of its critical electrical parameters after accelerated ageing tests is proposed and discussed. This study tend to explain the physical degradation mechanisms occurred during RF life-tests by means of 2D ATLAS-SILVACO simulations. Finally, the paper demonstrates that N-LDMOS degradation is linked to hot carriers generated interface states (traps) and trapped electrons, which results in a build up of negative charge at Si/SiO2 interface. More interface states are created at low temperature due to a located maximum impact ionization rate at the gate edge.     

On-wafer RF stress and trapping kinetics of Fe-doped AlGaN/GaN HEMTs

In this paper, we investigate the trapping effects, of iron doped AlGaN/GaN HEMTs, before and after on-wafer 24 hour RF stress test. First, we study the trap centers responsible of the current collapse at different on-state bias and temperature conditions. Second, we investigate 24 hour RF stress effect on the trapping kinetics.By filling traps under off-state condition with high drain-source voltage, we have identified two prominent traps labelled E₁ and E₂ with activation energies of 0.7 eV and 0.6 eV under the conduction band, respectively. An increase of the amplitude of the trap centers E₁ and E₂ by 22.9% and 15.8% respectively is noticed during the RF stress. This result suggests that the degradation observed during RF stress might have induced a density increase of the traps involved in the E₁ and E₂ trap signatures responsible on the current collapse.     

A robust and fast procedure for the determination of the small signal equivalent circuit of HEMTs

In this paper we present an analytical, fast, accurate and robust technique for the determination of the circuit model elements of HEMTs in the microwave range. By this method the values of the equivalent circuit parameters of the device under test are extracted using three measured scattering (S) parameter sets without any optimization. We also investigated the influence of the reverse transfer conductance Re(Y₁₂) on the modelling by means of a gate drain resistance R_dg. The validity of this method was verified upon a set of pseudomorphic HEMTs having different gate widths tested on wafer at several bias and temperature conditions. Very good agreement between the simulated and measured S-parameters has been obtained. The procedure has been implemented in Agilent VEE language as a fully automated tool to allow an accurate, fast and complete device characterization requiring no operator supervision.     

Influence of insulator thickness nonuniformity on the switching of the Al/SiO2/n-Si tunnel MOS structure at reverse bias

Current-voltage characteristics of the reversely biased Al/SiO₂/n-Si MOS structure are calculated taking into account the nonuniformity of oxide thickness distribution over an area at a nominal thickness of 1–3 nm. It is known that the characteristics are S-shaped in a certain range of average SiO₂ thickness, which suggests that a device is bistable. Holding and threshold voltage shifts, caused by statistical thickness variations, were predicted. In response to electrical stress, the root-mean-square deviation of the SiO₂ thickness increases, which results in a shift of the threshold voltage to higher values. The calculations are complemented by experimental data.