Simulated study on the InP/InGaAs DHBT under proton irradiation

A 3D model simulation of InP/InGaAs/InP DHBT is reported in this paper. A comprehensive set of built-in physical models are described, including Stratton''s hydrodynamic model, high-fields mobility model and thermionic emission model. A mixed-mode environment is required for AC simulation instead of simulating an isolated HBT, in which the HBT is embedded in an external circuit, and the circuit voltage and current equations are solved along with the Poisson equation and transport equations. In AC simulation, simulator Sentaurus provides the computation of the small signal admittance Y matrix. From the results of Y matrix, the small signal equivalent circuit is constructed with the conductance and capacitance obtained from Y matrix, and the AC parameters, such as S-parameters, will be calculated. The small signal AC characteristics of InP/InGaAs DHBTs under proton irradiation are simulated with different fluences of proton irradiation. Simulation results show that the maximum oscillation frequency will be degraded when fluence of proton irradiation is increased.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n -InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n -InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n -InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n+-InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n+-InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n+-InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

Preliminary results of storage accelerated aging test on InP/InGaAs DHBT

We report on the reliability of InP HBT technology which has applications in very high-speed ICs. This work presents the storage accelerated aging tests results performed on InP/InGaAs HBT at stress temperatures of 180, 210 and 240 °C up to 3000 h. We have performed aging tests for two generations of InP HBT which differ from the collector doping level and from material used for planarization. From the Gummel plots, we note that the major degradation mechanism is located at the base–emitter junction periphery. Investigations on the physical origin of the observed failure mechanism has been performed using TCAD simulations.     

Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design

The reliability of InP/InGaAs DHBT under high collector current densities and low junction temperatures is analyzed and modeled. From the Gummel characteristics, we observe several types of device degradation, resulting from the long term changes of base and collector current in both lower and higher base–emitter voltage ranges which impacts the reduction of DC current gain. In this paper, we investigate the underlying physical mechanism of base and collector current degradation with the help of TCAD device simulation. We chose the HICUM model level2 for the modeling purpose to evaluate the drift of model parameters according to stress time. The evolution of the model parameters is described with suitable equations to achieve a physics based compact electrical aging model. The aging laws and the parameter evolution equations with stress time are implemented in compact electrical aging model which allows us to simulate the impact of device failure mechanisms on the circuit in operating conditions.     

带有阶梯缓变集电区的InP/InGaAs/InP DHBT材料研究

设计并生长了一种新的InP/InGaAs/InP DHBT结构材料,采用在基区和集电区之间插入两层不同禁带宽度的InGaAsP四元系材料的阶梯缓变集电结结构,以解决InP/InGaAs/InP DHBT集电结导带尖峰的电子阻挡效应问题。采用气态源分子束外延(GSMBE)技术,通过优化生长条件,获得了高质量的InP、InGaAs以及与InP晶格相匹配的不同禁带宽度的InGaAsP外延材料。在此基础上,成功地生长出带有阶梯缓变集电区结构的InP基DHBT结构材料。     

Evaluation of encapsulation and passivation of InGaAs/InP DHBT devices for long-term reliability

Device encapsulation and passivation are critical for long-term reliability and stability. Several encapsulation techniques were evaluated in terms of degradation of electrical characteristics, gap filling under the mesa structures, and adhesion to the semiconductor and metal surfaces. These included plasma enhanced chemical vapor deposited (PECVD) SiO₂, electron cyclotron resonance CVD SiN_x, spin-on glass, benzocyclobutene, and polyimide. Damage from plasma exposure caused gain degradation in the devices. Spin-on coatings cause little to no gain degradation, provided that there is minimal stress in the cured film. SOG and BCB films have acceptable adhesion properties and were excellent for gap filling. Polyimide films have excellent adhesion properties, however, they were poor at gap filling and had a great deal of shrinkage during curing. Device passivation was evaluated using double heterojunction bipolar transistor structures with either an abrupt or graded emitter-base junction. Abrupt junction devices had the self-aligned base metal directly on the p⁺ InGaAs base. Graded junction devices had the base metal on top of graded InGaAsP layers, which the metal was diffused through, to make contact to the base region. Abrupt junction devices stressed at an initial J_E of 90 kA/cm² at a V_CE of 2V at 25°C degraded 20% within 70 h of operation, whereas, the graded junction devices show no degradation in dc characteristics after operation for over 500 h. Typical common emitter current gain was 50. An f_t of 80 and f_max of 155 GHz were achieved for 2×4 μm² emitter size devices.     

Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (S_EB) and base gap resistance (R_GAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced R_GAP, from 16.48 Ω to 4.62 Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (C_CB). Due to the reduced R_GAP, the maximum oscillation frequency (f_max) for a 0.5 μm-emitter HBT is improved from 205 GHz to 295 GHz, while the cutoff frequency (f_T) is maintained at around 300 GHz.     

InGaAs/InP DHBT technology and design methodology for over 40 Gb/soptical communication circuits

High-performance technologies and adequate design methodologies are required to address the needs of very high-speed ICs (VHSICs) for over 40 Gb/s optical communications. We describe improvements we have introduced in our InP DHBT technology, and how our design methodology has evolved, we show how it results in improved circuit designs, and present some recent results, with some considerations on measurement limitations     

Dry-etch fabrication of reduced area InGaAs/InP DHBT devices for high speed circuit applications

We have fabricated reduced area InGaAs/InP DHBTs for high speed circuit applications. To produce the small dimensions required, a process involving both wet chemical and ECR plasma etching was developed. Optical emission spectroscopy was used for end-point detection during plasma etching. With this improved process, an f_t of 170 and f_max of 200 GHz were achieved for 1.2 × 3 μm² emitter size devices with a 500 ? base.     

Novel fabrication of C-doped base InGaAs/InP DHBT structures for high speed circuit applications

We have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter–base and base–collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter–base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8-10 V, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in d.c. characteristics after operation at an emitter current density of 90 kA cm⁻² and a collector bias, V_CE, of 2 V at room temperature for over 500 h. Typical common emitter current gain was 50. An f_t of 80 and f_max of 155 GHz were achieved for 2×4 μm² emitter size devices.     

Comparison of InP/InGaAs DHBT distributed amplifiers as modulator drivers for 80-Gbit/s operation

This paper compares three single-ended distributed amplifiers (DAs) realized in an in-house InP/InGaAs double heterojunction bipolar transistor technology featuring an f/sub t/ and f/sub max/ larger than 200 GHz. The amplifiers use five or eight gain cells with cascode configuration and emitter follower buffering. Although the technology is optimized for mixed-signal circuits for 80 Gbit/s and beyond, DA results could be achieved that demonstrate the suitability of this process for the realization of modulator drivers. The results are documented with scattering parameter, eye diagram, and power measurements. This includes amplifiers featuring a 3-dB bandwidth exceeding 80 GHz and a gain of over 10 dB. One of the amplifiers exhibits clear eyes at 80 Gbit/s with a gain of 14.5 dB and a voltage output swing of 2.4 V/sub pp/ limited by the available digital input signal. This amplifier delivers an output power of 18 dBm (5.1 V/sub pp/) at 40 GHz and 1-dB compression. Two amplifiers offer a tunable gain peaking, which can be used to optimize circuit performance and to compensate losses in the circuit environment. The results show that, using our InP/InGaAs technology, an integration of high-speed mixed-signal circuits (e.g., multiplexers) and high-power modulator drivers on a single chip is feasible.     

Optimization of the base electrode for InGaAs/InP DHBT structures with a buried emitter-base junction

We have optimized the base electrode for InGaAs/InP based double heterojunction bipolar transistors with a buried emitter-base junction. For the buried emitter-base structure, the base metal is diffused through a thin graded quaternary region, which is doped lightly n-type, to make ohmic contact to the p⁺InGaAs base region. The metal diffusion depth must be controlled, or contact will also be made to the collector region. Several metal schemes were evaluated. An alloy of Pd/Pt/Au was the best choice for the base metal, since it had the lowest contact resistance and a sufficient diffusion depth after annealing. The Pd diffusion depth was easily controlled by limiting the thickness to 50?, and using ample Pt, at least 350?, as a barrier metal to the top layer of Au. Devices with a 500? base region show no degradation in dc characteristics after operation at an emitter current density of 90 kA/cm² and a collector bias, V_CE, of 2V at room temperature for over 500 h. Typical common emitter current gain was 120. An f_t of 95 GHz and f_max, of 131 GHz were achieved for 2×4 μm² emitter size devices.     

InGaAs/InP界面控制对InGaAs薄膜电学和光学性质 的影响

研究了全固态源分子束外延(MBE)生长InGaAs/InP异质结界面扩散对InGaAs外延薄膜电学和光学性质的影响.通过X射线衍射、变温霍尔测试和变温光致发光等方法对InGaAs薄膜样品进行细致研究.发现在InGaAs/InP界面之间插入一层利用As_4生长的InGaAs过渡层,能够显著改善上层InGaAs(利用As_2生长)外延薄膜的电学性能,其低温迁移率显著提高.同时荧光峰反常蓝移动消失,光学性质有所改善.研究表明利用As_4生长InGaAs过渡层,可显著降低As在InP中反常扩散,获得陡峭的InGaAs/InP界面,从而提高InGaAs材料电学和光学性能.     

Reliability of InGaAs/InP based separate absorption grading multiplication avalanche photodiodes

An overview over typical defects and reliability aspects regarding the operation of InGaAs/InP avalanche photodiodes for the use in fiber-optic communication systems is given.Measurements regarding the performance and stability of different types of top illuminated InGaAs/InP Separate Absorption Grading Multiplication avalanche photodiodes have been compared with special emphasis on the homogeneity of the photoresponse. High resolution scanning optical microscopy measurements at different wavelengths allowed to identify specific technological problems. Guard ring misalignment resulting in increased responsivity of the junction perimeter have been found on devices from one manufacturer.The responsivity images of the active area of some of the investigated photodiodes showed sharp peaks due to microplasma formation. The impact of these microplasmas on dark current and photocurrent of the devices has been investigated in detail.A step-stress test performed at successively increasing temperatures resulted in the catastrophic failure of the tested devices from one family. An analysis of the dark current-voltage characteristics before and after degradation leads to the conclusion that a modification of the semiconductor-insulator interface properties caused a dramatic increase in the surface leakage currents.     

DC and microwave noise transient behavior of InP/InGaAs doubleheterojunction bipolar transistor (DHBT) with polyimide passivation

DC and microwave noise transient behavior of InP/InGaAs double heterojunction bipolar transistor (DHBT) with polyimide passivation is reported in this paper for the first time. The base transient current is believed to be due to the change of surface potential near the base-emitter junction perimeter at the polyimide/emitter interface resulting from a decrease in the amount of trapped electrons in the polyimide. We also find that the surface potential on the sidewall of collector-emitter affected by the charge trapping and detrapping in polyimide may induce a parasitic polyimide field effect transistor along the surface of the base-collector junction which results in an excess collector transient current. These base and collector current transients result in associated transient of broadband shot noise. The time dependence of microwave noise figures due to the excess transients is also investigated. The better understanding of the mechanisms of the noise transient behavior of the InP HBT device is very useful to improve the device and circuit reliability     

Facet oxidation of InGaAsP/InP and InGaAs/InP lasers

The facet oxidation of InGaAsP/InP and InGaAs/InP lasers is investigated after aging under high constant optical output power or high current stress. Facet oxidation in InGaAsP/InP lasers is negligibly small under several thousand hours of practical operation. The thickness of oxide film increases in proportion to optical output power and logarithm of aging time. The growth rate of facet oxide film weakly depends on the junction temperature and the activation energy is estimated to be 0.07 eV within a experimental range between 25 and 150°C. The facet of InGaAs/InP lasers are oxidized more easily than that of InGaAsP/InP lasers but are about two orders of magnitude more stable against oxidation than that of AlGaAs/GaAs lasers.