共查询到20条相似文献,搜索用时 31 毫秒
1.
《Microelectronics Reliability》2014,54(11):2383-2387
This paper investigates voltage-dependent degradation of HfSiON/SiO2 nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime tL = 1.64 × 1010 s, which agreed well with the tL = 1.92 × 1010 s measured at low gate stress voltage, whereas the conventional model overestimates tL by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating tL of high-k nMOSFETs. 相似文献
2.
Masaoud Houshmand Kaffashian Reza Lotfi Khalil Mafinezhad Hamid Mahmoodi 《Microelectronics Reliability》2012,52(8):1655-1659
Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. This paper provides comprehensive analyses on the impacts of NBTI and PBTI on wide fan-in domino gates with high-k metal-gate devices. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG) are analyzed in the presence of NBTI/PBTI degradation. It has been shown that the main concern is the degradation impact on delay which can increase up to 16.2% in a lifetime of 3 years. We have also proposed a degradation tolerant technique to compensate for the NBTI/PBTI-induced delay degradation in domino gates with a negligible impact on UNG and power. 相似文献
3.
《Microelectronics Reliability》2014,54(9-10):1883-1886
Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the ON-resistance (RON) is observed. At stress times at which RON almost reaches its constant level, an increase of the drain leakage in OFF state (VDS = −60 V, VGS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS. 相似文献
4.
Generally it is known that NBTI degradation increases with decrease of a channel width in p-MOSFETs but hot carrier degradation decreases. In this work, a guideline for the optimum fin width in p-MuGFETs is suggested with consideration of NBTI and hot carrier degradation. Using the device lifetime defined as the stress time necessary to reach ΔVTH = 10 mV, the optimum fin widths have been extracted for different stress voltages and temperatures. When a fin width is narrower than the optimum fin width, the device lifetime is governed by the NBTI degradation. However, when fin width is wider than the optimum fin width, the device lifetime is dominantly governed by hot carrier degradation. The optimum fin width decreases with the increase of the stress voltage but it increases with the increase of the stress temperature. 相似文献
5.
We have systematically studied the effects of SixN1 − x passivation density on the reliability of AlGaN/GaN high electron mobility transistors. Upon stressing, devices degrade in two stages, fast-mode degradation and followed by slow-mode degradation. Both degradations can be explained as different stages of pit formation at the gate-edge. Fast-mode degradation is caused by pre-existing oxygen at the SixN1 − x/AlGaN interface. It is not significantly affected by the SixN1 − x density. On the other hand, slow-mode degradation is associated with SixN1 − x degradation. SixN1 − x degrades through electric-field induced oxidation in discrete locations along the gate-edges. The size of these degraded locations ranged from 100 to 300 nm from the gate edge. There are about 16 degraded locations per 100 μm gate-width. In each degraded location, low density nano-globes are formed within the SixN1 − x. Because of the low density of the degraded locations, oxygen can diffuse through these areas and oxidize the AlGaN/GaN to form pits. This slow-mode degradation can be minimized by using high density (ρ = 2.48 g/cm3) Si36N64 as the passivation layer. For slow-mode degradation, the median time to failure of devices with high density passivation is found to increase up to 2× as compared to the low density (ρ = 2.25 g/cm3) Si43N57 passivation. A model based on Johnson-Mehl-Avrami theory is proposed to explain the kinetics of pit formation. 相似文献
6.
This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO2/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO2 layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO2 and at the Si/SiO2 interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO2 layer increased. For the unexposed MOS devices, the flat band voltage VFB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance CDP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×1010 eV−1 cm−2. The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times. 相似文献
7.
A. Veloso H.Y. Yu A. Lauwers S.Z. Chang C. Adelmann B. Onsia M. Demand S. Brus C. Vrancken R. Singanamalla P. Lehnen J. Kittl T. Kauerauf R. Vos B.J. O′Sullivan S. Van Elshocht R. Mitsuhashi G. Whittemore K.M. Yin M. Niwa S. Biesemans 《Solid-state electronics》2008,52(9):1303-1311
This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (1) both cases result in dielectric modification with gate leakage (JG) reduction; (2) adding a cap has no significant impact on Tinv(<1 Å), while up to ~5 and 2 Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively, (3) the largest JG reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in JG and mobility but with 500 mV smaller VT; (4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; (5) excellent process control and reliability behavior (VT instability by a.c. pulsed IV, PBTI and TDDB) is reported for both eWF tuning methods. They allow ΔeWF(n?p) values up to ~800 meV when combined with Ni–silicide FUSI phase engineering, promising for low-VT CMOS. 相似文献
8.
F. Rochette X. Garros G. Reimbold F. Andrieu M. Cassé M. Mouis G. Ghibaudo F. Boulanger 《Microelectronic Engineering》2009,86(7-9):1897-1900
The impact of biaxial stress on gate leakage is investigated on fully-depleted silicon-on-insulator (FD-SOI) nMOS transistors, integrating either a standard gate stack or an advanced high-κ/metal gate stack. It is demonstrated that strained devices exhibit significantly reduced leakage currents (up to ?90% at Eox = 11 MV/cm for σtensile = 2.5 GPa). This specific effect is used to extract the conduction band offset ΔEc induced by strain and is shown to be accurate enough to monitor stress in MOSFETs. This new technique is much less sensitive to gate oxide defects than the method based on the threshold voltage shift ΔVT. This accurate experimental extraction allowed us to pick out realistic values for the deformation potentials in silicon (Ξu = 8.5 eV and Ξd = ?5.2 eV), among the published values. 相似文献
9.
C. Le Royer L. Clavelier C. Tabone K. Romanjek C. Deguet L. Sanchez J.-M. Hartmann M.-C. Roure H. Grampeix S. Soliveres G. Le Carval R. Truche A. Pouydebasque M. Vinet S. Deleonibus 《Solid-state electronics》2008,52(9):1285-1290
We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart CutTM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION, IOFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μh ~ 250 cm2/V/s, ION = 436 μA/μm for LG = 105 nm), and OFF current densities comparable or better than those reported in the literature. 相似文献
10.
We have modeled and characterized scaled Metal–Al2O3–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (KA = 9) blocking insulator of ALD deposited Al2O3 (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 1018 traps/cm3 eV. The devices show excellent endurance with no memory window degradation to 106 write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices. 相似文献
11.
《Solid-state electronics》2006,50(9-10):1667-1669
In this paper, we present a new Polysilicon–Aluminum Oxide–Nitride–Oxide–Silicon (SANOS) device structure suitable for future nonvolatile semiconductor memories. Replacing SiO2 with a high-K material, Al2O3 (Kf = 9) as the top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer with its dielectric constant during write and erase operations. Therefore, this new device can achieve lower programming voltages and faster programming speed than the conventional SONOS device. We have fabricated SANOS capacitors with 2 nm tunnel oxide, 5 nm silicon nitride and 8 nm aluminum oxide and studied the programming speed and charge retention characteristics of the new devices. These new SANOS devices achieve a 2 V reduction in the programming voltages with 2.1 V initial memory window. 相似文献
12.
This paper proposes a fast and accurate method to measure the constants a and n of the power law ∆ Vth = atn for HfSiON/SiO2 dielectric nMOSFETs under positive bias temperature instability (PBTI), where ∆ Vth is a shift of threshold voltage, and t is stress duration. The proposed method requires one nMOSFET only, uses a voltage ramp stress (VRS), measures ∆ Vth vs. t data during VRS, uses a regression method to fit the data for each VRS pulse to the power law to obtain a and n at each stress voltage Vg,str, then obtains five voltage-independent constants for the power law after fitting the curves of a and n vs. Vg,str to empirical models. The five voltage-independent constants agreed very well with those obtained using the constant voltage stress (CVS) method. After obtaining the voltage-independent constants, the lifetime tL at an operating voltage Vop was estimated using the power law. The estimated tL = 1.67 × 108 s was quite close to tL = 1.74 × 108 s estimated using CVS, and to tL = 1.72 × 108 s estimated by extrapolating the ΔVth vs. t curve measured at Vg,str = Vop = 1.2 V to ΔVth = 200 mV. The time required for measurement was 900 s, compared to 30,000 s for the CVS method. These experimental results show that the proposed VRS-regression method is very useful for screening nMOSFETs under PBTI. 相似文献
13.
The linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed in long channel nanowire MOSFETs with different fin width (WFIN), from quasi-planar structures (WFIN = 10 μm) to narrow devices (9.5 nm), operating as single-transistor amplifiers from room temperature down to 100 K. The total, second and third order harmonic distortions (THD, HD2 and HD3, respectively) are extracted using the Integral Function Method (IFM). The analysis is divided in two parts. First, a fixed input signal is applied at the gate of the single-transistor amplifiers and, then, the output signal is fixed. Transport parameters such as effective mobility (μeff), mobility degradation coefficient (θ) and series resistance (RS) have been extracted down to 100 K and correlated to the distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors have shown improved linearity mainly due to higher intrinsic voltage gain (AV) considering the entire temperature range. Low temperature operation has shown to degrade the linearity characteristics of both wide and narrow NW MOSFETs. 相似文献
14.
With technologies scaling down to 28 nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO2 film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times. 相似文献
15.
Chien-Wei Liu Chin-Lung Cheng Kuei-Shu Chang-Liao Jin-Tsong Jeng Bau-Tong Dai Chen-Pang Tsai 《Microelectronic Engineering》2009,86(7-9):1692-1695
Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiOxNy metal oxide NPs embedded in the HfOxNy high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O2/N2 ambient. Well-isolated TiOxNy NPs with a diameter of 5–20 nm, a surface density of ~3 × 1011 cm?2, and a charge trap density of around 2.33 × 1012 cm?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping. 相似文献
16.
Emilie Bernard T. Ernst B. Guillaumot N. Vulliet X. Garros V. Maffini-Alvaro P. Coronel T. Skotnicki S. Deleonibus 《Solid-state electronics》2008,52(9):1297-1302
In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO2, TiN/SiO2 or N+ poly-Si/SiO2 are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO2 gate stack demonstrates the best ION/IOFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V. 相似文献
17.
C.P. Chen T.D. Lin Y.J. Lee Y.C. Chang M. Hong J. Kwo 《Solid-state electronics》2008,52(10):1615-1618
A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In0.2Ga0.8As on GaAs using TiN as gate metal and Ga2O3(Gd2O3) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at Vg = 4 V and Vd = 2 V, a low gate leakage of <10?7 A/cm2 at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at Vg = 3 V, Vd = 2 V, and an on/off ratio of ~105 in drain current. For comparison, a TiN/Ga2O3(Gd2O3)/In0.2Ga0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10?8–10?9 A/cm2, well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ~16 and a low interfacial density of state of ~(2~6) × 1011 cm?2 eV?1, and an atomically sharp smooth Ga2O3(Gd2O3)/In0.2Ga0.8As interface. 相似文献
18.
《Solid-state electronics》2006,50(9-10):1551-1556
In this paper, based on a precise and efficient analytical function of relatively realistic dopant fluctuations, a new method is proposed to simulate the threshold voltage variation of MOSFET’s with non-uniform channel doping due to random dopant fluctuations. Both the number and position fluctuations of dopants are taken into account. Using this method, 2500 microscopically different devices under certain process conditions that cover the range of channel length L from 35 nm to 90 nm, oxide thickness Tox from 1 nm to 4 nm and channel surface doping concentration NA from 1 × 1018 to 5 × 1018 cm−3 are simulated to show how our method works. 相似文献
19.
This paper proposes a method which can separate the parasitic effect from the drain current Id vs. gate voltage Vg curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An Id vs. Vg curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of Id vs. channel width W at each Vg to W = 0 μm. The Id vs. Vg curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage Vth of the parasitic MOSFET but increased Vth of the main MOSFET. These two opposite behaviors of Vth resulted in little HEIP-induced shift of Vth at W = 2.5 μm. | Vd | to secure ten-year HEIP lifetime of 10% shift of Vth was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly. 相似文献
20.
《Microelectronics Journal》2014,45(2):144-151
Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO2) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (gm), output conductance (gd), transconductance generation factor (gm/ID), early voltage (VEA), intrinsic gain (AV), cut off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V−1, 39.589 V−1) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×105 GHz/V, 1.72×105 GHz/V) for two different values of VDS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5. 相似文献