NMOS管热载流子衰退效应评价模型及寿命预测方法研究

热载流子是器件可靠性研究的热点之一.特别对于亚微米器件,热载流子失效是器件失效的一个最主要方面.通过对这种失效机理及其失效模型的研究,为设计和工艺提供帮助,从而有效降低由热载流子引起的电路失效,提高电路可靠性.本文主要针对几种典型工艺的栅氧厚度(例如:Tox分别为150 (A)、200 (A)、250 (A))的NMOSFET进行加速应力实验,提取寿命模型的相关参数,估算这些器件在正常工作条件下的寿命值,对亚微米工艺器件寿命进行快速评价.     

不同栅氧厚度NMOS管的热载流子效应

文章主要讨论在相同工艺条件下,针对不同栅氧厚度(例如:Tox分别为150A、200A、 250A)的NMOSFET进行加速应力试验,在试验中当某些参数的漂移量达到失效判据规定的值时(例如:阈值电压改变50mV),可以得到器件的应力寿命,由此估计该器件在正常工作条件下的寿命值, 并对该工艺的热载流子注入效应进行评价。     

GIDL应力下超薄栅氧LDD NMOS器件退化

The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

总剂量辐照对65 nm NMOSFET热载流子敏感参数的影响

为了研究总剂量辐射对纳米MOS晶体管热载流子效应的影响,对65 nm 体硅工艺的NMOS器件进行了总剂量辐射和热载流子试验,对比了辐射前后不同宽长比器件的跨导、栅极泄漏电流、线性饱和电流等电参数。结果表明,MOS器件的沟道宽度越窄,热载流子效应受辐射的影响越显著,总剂量辐射后热载流子效应对器件的损伤增强。分析认为,辐射在STI中引入的陷阱电荷是导致以上现象的主要原因。该研究结果为辐射环境下器件的可靠性评估提供了依据。     

Modeling of threshold voltage of a quadruple gate transistor

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. For numerical simulation, self-consistent Schrodinger-Poisson equations, calibrated by 2D non equilibrium green function simulation, are used. This analytical model not only provides useful physics insight of effects of gate length and body width on the threshold voltage, but also serves as a basis for compact modeling of quadruple gate MOSFETs.     

Physically-based threshold voltage determination for MOSFET's ofall gate lengths

A reliable method to determine the threshold voltage V_th for MOSFETs with gate length down to the sub-0.1 μm region is proposed. The method determines V_th by linear extrapolation of the transconductance g_m to zero and is therefore named “GMLE method”. To understand the physical meaning of the method and to prove its reliability for different technologies 2-D simulation was applied. The results reveal that determined V_th values always meet the threshold condition, i.e., the onset of inversion layer buildup     

High air stability of threshold voltage on gate bias stress in pentacene TFTs with a hydroxyl-free and amorphous fluoropolymer as gate insulators

We investigated the air stabilities of threshold voltages (V_th) on gate bias stress in pentacene thin-film transistors (TFTs) with a hydroxyl-free and amorphous fluoropolymer as gate insulators. The 40-nm-thick thin films of spin-coated fluoropolymer had excellent electrical insulating properties, and the pentacene TFTs exhibited negligible current hysteresis, low leakage current, a field-effect mobility of 0.45 cm²/Vs and an on/off current ratio of 3 × 10⁷ when it was operated at −20 V in ambient air. After a gate bias stress of 10⁴ s, a small V_th shift below 1.1 V was obtained despite non-passivation of the pentacene layer. We have discussed that the excellent air stability of V_th was attributed to the insulator surface without hydroxyl groups.     

N-LDMOS热载流子注入效应的分析和优化

研究了一种N-LDMOS器件的热载流子注入效应,分析了热载流子效应产生的机理、对器件性能以及可靠性的影响,提出了改进方法.为了降低此器件的热载流子注入效应,我们利用华润上华公司提供的ISE软件对N-LDMOS高压工艺进行模拟,根据模拟结果调整了器件结构,通过增大器件的场板长度、漂移区长度以及增加N阱与有源区的交叠长度等措施,使得相同偏置条件下,表征热载流子注入强度的物理量——器件衬底电流降为改进前的1/10,显著改善了该器件的热载流子注入效应.     

MOSFET的热载流子损伤及其退火

对国内常规54HC工艺制作的PMOSFET进行了F-N热载流子注入损伤实验,研究了MOSFET跨导、阈电压等参数随热载流子注入的退化规律,特别是从微观氧化物电荷和界面态变化对阈电压影响角度,对国内外较少见报道的MOSFET热载流子损伤在室温和高温(100°C)下的退火特性进行了研究,并从该角度探讨了MOSFET热载流子注入产生氧化物电荷和界面态的特性。     

多层浮栅FET pH传感单元阈值电压敏感模型分析和讨论

Research into new pH sensors fabricated by the standard CMOS process is currently a hot topic. The new pH sensing multi-floating gate field effect transistor is found to have a very large threshold voltage, which is different from the normal ion-sensitive field effect transistor. After analyzing all the interface layers of the structure, a new sensitive model based on the Gauss theorem and the charge neutrality principle is created in this paper. According to the model, the charge trapped on the multi-floating gate during the process and the thickness of the sensitive layer are the main causes of the large threshold voltage. From this model, it is also found that removing the charge on the multi-floating gate is an effective way to decrease the threshold voltage. The test results for three different standard pH buffer solutions show the correctness of the model and point the way to solve the large threshold problem.     

Channel width dependence of NMOSFET hot carrier degradation

The channel width dependence of hot carrier reliability on NMOSFETs from 0.4-/spl mu/m to 0.13-/spl mu/m technology has been studied at both I/sub b,peak/ and V/sub g/ = V/sub d/ conditions. Enhanced degradation on narrow width devices happens on most technologies. The I/sub b//I/sub d/ value and vertical electric field are proposed to be the reasons for enhanced degradation on narrow width NMOSFETs.     

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.     

基于重复测试和栅压应力测试的石墨烯晶体管回滞特性的研究

The current transport characteristic is studied systematically based on a back-gate graphene field effect transistor, under repeated test and gate voltage stress. The interface trapped charges caused by the gate voltage sweep process screens the gate electric field, and results in the neutral point voltage shift between the forth and back sweep direction. In the repeated test process, the neutral point voltage keeps increasing with test times in both forth and back sweeps, which indicates the existence of interface trapped electrons residual and accumulation. In gate voltage stress experiment, the relative neutral point voltage significantly decreases with the reducing of stress voltage, especially in -40 V, which illustrates the driven-out phenomenon of trapped electrons under negative voltage stress.     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation.