A Model for Understanding Electromigration-Induced Void Evolution in Dual-Inlaid Cu Interconnect Structures

Electromigration-induced void evolution in various dual-inlaid copper (Cu) interconnect structures was simulated by applying a phenomenological model assisted by Monte Carlo-based simulations, considering the redistribution of heterogeneously nucleated voids and/or pre-existing vacancy clusters at the Cu/dielectric cap interface during electromigration. The results indicate that this model can qualitatively explain the electromigration-induced void evolution observed during experimental in situ secondary-electron microscopy (SEM) investigations as well as in various other reported studies. The electromigration mechanism in Cu interconnect structures and differences in the peculiar electromigration-induced void evolution in various dual-inlaid Cu interconnect structures can be clearly understood based on this model. These findings warrant reinvestigation of technologically important electromigration mechanisms by developing rigorous models based on similar concepts.     

Morphology of electromigration-induced damage and failure in Al alloy thin film conductors

Distinct morphologies of electromigration-induced voids and failures are shown for Al, Al-2%Cu, and Al-2%Cu-l% Si narrow (1–6 μm) unpassivated thin film conductors. SEM and TEM images typically show large non-fatal voids and narrow slit-like open circuit failures for all film conditions and accelerated test conditions. Evidence for transgran-ular slit failures is shown for 1.33 μm wide conductors. A simple model for void growth is presented which accounts for the void morphologies seen. The observed morphologies and the results of void growth modelling suggest that slit voids nucleate after other voids and rapidly produce failure. These conclusions are discussed in terms of ‘classical’ models for electromigration failure processes and resistance and noise power monitoring techniques.     

Surface electromigration in copper interconnects

RF-magnetron sputter deposited copper films have been characterised in terms of microstructure, stress and resistivity. The electromigration behaviour of this copper has been compared to that of sputtered aluminium. Atomic Force Microscopy has been used to study the void sites. The morphology of the damaged regions, together with the microstructural information, has been used to gain an insight into the mechanism by which electromigration voiding proceeds. The observed void sites in copper are entirely different from those in aluminium; hence a different failure mechanism must be responsible. The voiding process for copper can be explained by a grain-boundary grooving model, and it was observed that surface impurities controlled the damage mechanism and the resulting void morphology.     

Analysis of the reservoir effect on electromigration reliability

The reservoir effect on electromigration reliability is analyzed using the normalized vacancy concentration distribution in the reservoir region of multi-level Al–0.5%Cu interconnect structure. With the assumption of steady state for the vacancy concentration and the fact that no current flow conducts in the reservoir region during electromigration test, a simple equation for calculation of the vacancy concentration is induced. Then direct calculation of the equation is carried out utilizing the hydrostatic stress distribution computed from finite element method to estimate the probability of initial void formation in the reservoir region. Finally, three multi-level Al–0.5%Cu interconnect structures with different reservoir lengths are constructed and electromigration lifetime for the structures is measured to clarify these computational results. From the results of this study, we conclude that the normalized vacancy concentration under the assumption of steady state can be regarded as a quantitative parameter to analyze the reservoir effect on electromigration reliability.     

The influence of TiN ARC thickness on stress-induced void formationin tungsten-plug vias

This paper describes a new failure mechanism in W-plug vias, and the process conditions which enhance it. For submicron technologies, the limiting factor in interconnect reliability performance is increasingly dominated by the electromigration resistance of tungsten-plug vias. We have observed that under certain experimental conditions, early electromigration failures can be induced in via-chain test structures. We have demonstrated that these are caused by stress-induced void formation in the metal line immediately beneath the tungsten plug. This is thought to be due to highly localized film stress around the base of the plug, which can be minimized by increasing the thickness of the TiN anti-reflective coating (ARC). This has the effect of reducing the incidence of early failure by suppressing the stress-induced failures     

Studies on solder bump electromigration in Cu/Sn–3Ag–0.5Cu/Cu system

This paper aims to understand the solder bump electromigration phenomenon in the Cu/Sn–3Ag–0.5Cu/Cu system. A temperature of 453 K with a current density of 10 kA/cm² was applied. A void nucleated at the highest current density point at the cathode. As the void grew along the cathode side, a solder depletion occurred on the opposite side of the electron entry point, resulting in an open failure. A unique purposely-designed 3D model simulation methodology provides a good understanding of the void nucleation and growth behavior. The temperature of the solder joint during the electromigration test was measured successfully by the resistance change in the junction line between the two joints.     

Analysis of electromigration induced early failures in Cu interconnects for 45 nm node

Bi-directional current stressing was used for monitoring electromigration (EM) lifetime evolution in 45 nm node interconnects. Experimental results show that an initial bimodal distribution of lifetimes can be modified into a more robust mono-modal distribution. Since the bi-directional tests provide successive void nucleation and void healing phases, the Cu microstructure is thought to evolve once the formed void is filled thanks to EM induced matter displacement. FEM modeling is used to compare the predicted location of void nucleation for given microstructures at the cathode end: a multigrain structure is compared to a perfect bamboo microstructure. Experimental and modeling results let us assume that small grains (<linewidth or via diameter) at the cathode end present a risk of EM induced early fails. Indeed at this location void nucleates and grows nearby the via opening it shortly. On the contrary, the bamboo microstructure is thought to provide more robust lifetime because voids nucleate a few hundred nanometers in the line and grow down reaching the bottom diffusion barrier of the line. This latter case provides larger void size before circuit opening.     

Electromigration Damage Characterization in Sn-3.9Ag-0.7Cu and Sn-3.9Ag-0.7Cu-0.5Ce Solder Joints by Three-Dimensional X-ray Tomography and Scanning Electron Microscopy

Cerium (Ce)-containing Sn-3.9Ag-0.7Cu alloy exhibits desirable attributes of microstructural refinement, increased ductility, and mechanical shock performance, while possessing better oxidation resistance than other rare-earth-containing solders. In addition to the beneficial mechanical properties, it is imperative to study the reliability performance of novel solder alloys in the form of electromigration experiments, in comparison with Sn-3.9Ag-0.7Cu. In this study, electromigration tests were conducted on solder joints at elevated temperature with a constant current using a V-groove testing methodology. The microstructural change of solder joints during electromigration was investigated by scanning electron microscopy, and the void growth was monitored utilizing the three-dimensional (3D) x-ray microtomography imaging technique. The current density inside the solder matrix was determined by 3D microstructure-based finite-element modeling. Finally, the product of diffusivity and effective charge number of solder joints during electromigration was calculated from both marker displacement and 3D void growth. It was found that electromigration-induced Cu diffusion in Sn-3.9Ag-0.7Cu-0.5Ce alloy was greatly accelerated, and void formation at the cathode side was retarded as a result of finer microstructure and existence of CeSn₃ intermetallic particles.     

Early electromigration effects and early resistance changes

This paper reviews different known physical phenomena acting during electromigration, such as changes in the mechanical stress of the metal line, void growth and precipitation/dissolution of alloy elements (Cu, Si) and their effects on early resistance changes. The superposition of all these phenomena is also discussed to describe the typical early resistance changes detected in Al–Cu lines of the present technology.     

Experimental characterization and modelling of electromigration lifetime under unipolar pulsed current stress

The electromigration behaviour of Cu/SiCOH interconnects carrying unipolar pulsed current with long periods (i.e. 2, 16, 32 and 48 h) is presented in this study. Experimental observations suggest that the electromigration behaviour during void growth can be described by the ON-time model and that the lifetime of the Cu/SiCOH interconnects is inversely related to the duty cycle. Numerical simulation is carried out to compute the time required to nucleate a void under unipolar pulsed current stress conditions. The time to void nucleation is found to vary proportionally to the inverse square of the duty cycle and is independent of frequency at 1 Hz and higher. By computing the stress evolution in interconnects with short length, it was shown that the product of the unipolar pulsed current’s duty cycle and current density, i.e. average current density, is equivalent to the current density of a constant current (D.C.) stress. The simulation results suggest (d · jL)_crit as the equivalent critical current density-length product under unipolar pulsed current condition. Both the experimental and simulation results show that duty cycle has an effect on the electromigration lifetime of interconnects carrying unipolar pulsed current.     

The blocking barrier effect on aluminum electromigration due totitanium layers in multilayered interconnects of LSI's

Experimental evidence of an increase in the resistance of a cathode-side metal line without any void generation is presented for a multilayered metal structure terminated by via-holes during electromigration tests. This resistance increase is reversed to the initial value by high temperature storage after electromigration testing. The increase in the resistance of multilayered metal structures is attributed to the vacancy accumulation in the cathode side due to the blocking barrier effect of the refractory metal layer in the via-hole     

Electromigration lifetimes and void growth at low cumulative failure probability

We have investigated electromigration (EM) lifetimes and void formation at cumulative failure probability of around 50 ppm. We carried out EM test in damascene Cu lines using sudden-death test structures. Cumulative failure probability of the test ranges from 50 ppm to 90%. To investigate the void nucleation and growth behaviour, Cu microstructures were investigated by using scanning transmission electron microscopy (S-TEM) and electron backscatter diffraction (EBSD) technique. EM lifetime shows strong correlation with the void nucleation site and the void volume. In addition, the worst case for EM lifetime is that wide angle grain boundary exists just under the via as a void nucleation site.     

Nano- and micrometer-scale thin-film-interconnection failure theory and simulation and metallization lifetime prediction,Part 2: Polycrystalline-line degradation and bulk failure

The degradation and bulk failure of a polycrystalline interconnect line caused by vacancy electromigration along grain boundaries and vacancy-cluster nucleation at triple points in the bulk conductor are investigated within the general theory of the electromigration-induced degradation and failure of thin-film on-chip interconnect lines, presented in Part 1 [1]. The general equations are tailored to deal with vacancy electromigration, mechanical-stress generation, and void nucleation at triple points. Appropriate boundaryvalue problems are formulated, and numerical methods and procedures to solve them are developed and implemented in software. Computer simulations are performed to identify a pattern of electromigration failure at triple points. On this basis, (1) interconnect lifetime is investigated over wide ranges of variation of material, structural, geometric, and operating parameters, and (2) the current-density and temperature dependence—of the mechanical stress, vacancy concentration, and level of vacancy supersaturation at a triple point, and of void radius and time to nucleation-is examined and explained. The simulation results are found to agree well with previous experiments. This investigation could be seen as a natural continuation of our study of electromigration failures developed by multilevel-metallization systems as a result of interconnect failure near via junctions or at open ends [1]. Together they cover most mechanisms of electromigration failure suffered by metallization systems.     

Effect of Migration and Condensation of Pre-existing Voids on Increase in Bump Resistance of Flip Chips on Flexible Substrates during Electromigration

In Pb-free solder joints formed by reflowing a bump of solder paste, voids are formed within the solder due to the residue of flux in the reflow process. These voids migrate toward the cathode contact during electromigration under current stressing. Accompanying the electromigration, resistance jumps of a few 100 mΩ were observed. It was postulated that a jump occurs when a void touches the cathode contact. This study investigated the effect of the void migration and condensation on the change in bump resistance using three-dimensional (3D) simulations and finite element analysis. It was found that there was negligible change in bump resistance during void migration towards the high-current-density region before touching the cathode contact opening. When a small void condensed on the contact opening and depleted 18.4% of the area, the bump resistance increased only 0.4 mΩ. Even when a large void depleted 81.6% of the opening, the increase in bump resistance was 3.3 mΩ. These values are approximately two orders of magnitude smaller than those reported in the literature for the change in resistance due to void migration in flip chips on flexible substrates. We conclude that the reported change in resistance was most likely that of the Al or Cu interconnection in the flip-chip samples.     

Study of EM void nucleation and mechanic relaxation effects

In this paper the void formation during electromigration is characterized with the single standard via (SSV) and the innovative local sense structure (LSS). LSS allows the measurement of small resistance change before the final void formation. This has allowed to define a time nucleation for the void. The SSV has been used to study: side effect in the first phase (i.e. the “plateau”), the time to failure (TTF) and the void growth. The comprehension of all these phenomena will be fundamental for the future of interconnects reliability physics and lifetime prediction.     

Electromigration-induced damage in bamboo Al interconnects

Depletion and hillock formation were examined in-situ in a scanning electron microscope (SEM) during electromigration of bamboo Al interconnect segments. Hillocks formed directly at the anode ends of the segments by epitaxial addition of Al at the bottom Al/TiN interface. Depletion occurred nonuniformly from the cathode end and stopped once the distance between the leading void and the hillock reached the critical length for electromigration at the given current density. A modified equation for the drift velocity is proposed, which includes the effect of nonuniform depletion and predicts that interconnects with nonuniform depletion are more reliable than those with uniform depletion.     

Combined low-frequency noise and resistance measurements for void extraction in deep-submicrometer interconnects

Electromigration stress can give rise to voids that increase the resistance and localized thermal stress in interconnects. Estimation of the extent of voiding can provide information on the material quality and the amount of degradation that has resulted from the electrical stress. In this paper, a model is proposed that can be used to estimate the effective void volume in deep-submicrometer interconnects. The model uses a combination of low-frequency noise and resistance measurements, and also considers the thermal coefficient of resistance in calculating the change in resistance of the interconnect line. A deconvolution scheme was employed to extract the 1/f noise component from the noise-measurements to improve the accuracy of the extraction algorithm. To verify the accuracy of the model, the focused ion beam (FIB) technique was used to mill holes (to simulate voids) of known dimensions. The model was further applied to an electromigration stress study of aluminum (Al) interconnects as a method of testing its validity for stress-induced voids. The proposed technique is a useful reliability tool for void detection in deep-submicrometer interconnects.     

Skin effect of on-chip copper interconnects on electromigration

A simple model is derived to evaluate skin effect of on-chip copper interconnects on electromigration. The result gives the range of frequency in which skin effect on electromigration need to be taken into consideration.     

The evolution of the resistance of aluminum interconnects during electromigration

Resistance monitoring is a traditional method to investigate electromigration failure. It is important to understand how much information can be extracted from the data generated by these experiments. To this end, precision resistance measurements were included as part of accelerated electromigration tests performed inside of a high voltage scanning electron microscope (HVSEM). Twenty-two passivated Al interconnects were tested at 30 mA/μm² and at two temperatures, half at 212°C and half at 269°C. During every test, our automated apparatus stored images of each 300 μm long structure several times per hour. The resistance of each line was also precisely measured and recorded. Changing the temperature affected only the time scale of the resistance evolution. There were resistance changes before voids formed that were neither due to temperature fluctuations nor solute effects. In most cases, the nucleation of the first void to form in a line was signaled by an increase in the time derivative of the resistance. Due to the strong effect of void shape, the void volume could not be determined by the magnitude of the resistance change. The width of a void (transverse to the line) rather than the volume largely determined the resistance change.     

Recent advances on kinetic analysis of electromigration enhanced intermetallic growth and damage formation in Pb-free solder joints

A comprehensive kinetic analysis was established to investigate the electromigration (EM) enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints with Cu under bump metallization (UBM). The kinetic model takes into account Cu-Sn interdiffusion and current stressing. Derivation of the diffusion coefficients and the effective charge numbers for the intermetallic compounds is an essential but challenging task for the study of this multi-phase multi-component intermetallic system. A new approach was developed to simultaneously derive atomic diffusivities and effective charge numbers based on simulated annealing (SA) in conjunction with the kinetic model. A consistent set of parameters were obtained, which provided important insight into the diffusion behaviors driving the IMC growth. The parameters were used in a finite difference model to numerically solve the IMC growth problem and the result accurately correlated with the experiment. EM reliability test revealed that the ultimate failure of the solder joints was caused by extensive void formation and subsequent crack propagation at the intermetallic interface. This damage formation mechanism was analyzed by first considering vacancy transport under current stressing. This was followed by a finite element analysis on the crack driving force induced by void formation. This paper is concluded with a future perspective on applying the kinetic analysis and damage mechanism developed to investigate the structural reliability of the through-Si-via in 3D interconnects.