Low-voltage,high speed inkjet-printed flexible complementary polymer electronic circuits

We report the development of high-performance inkjet-printed organic field-effect transistors (OFETs) and complementary circuits using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) for high-speed and low-voltage operation. Inkjet-printed p-type polymer semiconductors containing alkyl-substituted thienylenevinylene (TV) and dodecylthiophene (PC12TV12T) and n-type P(NDI2OD-T2) OFETs showed high field-effect mobilities of 0.1–0.4 cm² V^?1 s^?1 and low threshold voltages down to 5 V. These OFET properties were modified by changing the blend ratio of P(VDF-TrFE) and PMMA. The optimum blend – a 7:3 wt% mixture of P(VDF-TrFE) and PMMA – was successfully used to realize high-performance complementary inverters and ring oscillators (ROs). The complementary ROs operated at a supplied bias (V_DD) of 5 V and showed an oscillation frequency (f_osc) as high as ～80 kHz at V_DD = 30 V. Furthermore, the f_osc of the complementary ROs was significantly affected by a variety of fundamental parameters such as the electron and hole mobilities, channel width and length, capacitance of the gate dielectrics, V_DD, and the overlap capacitance in the circuit configuration.     

Ultra-thin polymer gate dielectrics for top-gate polymer field-effect transistors

We have demonstrated top-gate polymer field-effect transistors (FETs) with ultra-thin (30–50 nm), room-temperature crosslinkable polymer gate dielectrics based on blending an insulating base polymer such as poly(methyl methacrylate) with an organosilane crosslinking agent, 1,6-bis(trichlorosilyl)hexane. The top-gate polymer transistors with thin gate dielectrics were operated at gate voltages less than ?8 V with a relatively high dielectric breakdown strength (>3 MV/cm) and a low leakage current (10–100 nA/mm² at 2 MV/cm). The yield of thin gate dielectrics in top-gate polymer FETs is correlated with the roughness of underlying semiconducting polymer film. High mobilities of 0.1–0.2 cm²/V s and on and off state current ratios of 10⁴ were achieved with the high performance semiconducting polymer, poly(2,5-bis(3-alkylthiophen-2yl)thieno[3,2-b]thiophene.     

Dielectric surface-polarity tuning and enhanced operation stability of solution-processed organic field-effect transistors

The electrical performance of triethylsilylethynyl anthradithiophene (TES-ADT) organic field-effect transistors (OFETs) was significantly affected by dielectric surface polarity controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH₃)₂Cl) to 300-nm-thick SiO₂ dielectrics. On the untreated and treated SiO₂ dielectrics, solvent–vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The operation and bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with a decrease in dielectric surface polarity. Among dielectrics with similar capacitances (10.5–11 nF cm⁻²) and surface roughnesses (0.40–0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and a charge-carrier mobility ∼1.32 cm² V⁻¹ s⁻¹, on–off current ratio >10⁶, threshold voltage ∼0 V, and long-term operation stability under negative bias stress.     

Integration of Gd silicate/TiN gate stacks into SOI n-MOSFETs

In this work we describe the gate first integration of gadolinium silicate (GdSiO) high-k dielectrics and metal gate electrodes into SOI n-MOSFETs. Fully functional devices are achieved and compared to reference devices with standard SiO₂. Analysis of electron transport in these gate stacks is performed by specific MOSFET test structures that enable extraction of intrinsic inversion channel mobility. Attractive peak mobilities of 170 cm²/Vs have been found for GdSiO.     

Controllable carrier density of pentacene field-effect transistors using polyacrylates as gate dielectrics

We have studied the effect of the chemical structure of dielectrics by evaporating pentacene onto a series of polyacrylates: poly(methylmethacrylate), poly(4-methoxyphenylacrylate), poly(phenylacrylate), and poly(2,2,2-trifluoroethyl methacrylate) in organic thin-film transistors (OTFTs). In top-contact OTFTs, the polyacrylates had a significant effect on field-effect mobilities ranging 0.093 ∼ 0.195 cm² V⁻¹ s⁻¹. This variation neither correlated with the polymer surface morphology nor the observed pentacene crystallite size. This result implies that the PTFMA device generates the local electric field that accumulates holes and significantly shifts the threshold voltage and the turn-on voltage to −8.62 V and 3.5 V, respectively, in comparison with those of PMMA devices.     

Novel organic inverters with dual-gate pentacene thin-film transistor

We report on the fabrication and characterization of dual-gate pentacene organic thin-film transistors (OTFTs) with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al₂O₃ as a bottom-gate dielectric and PEALD 200 nm thick Al₂O₃ as a top-gate dielectric. The V_th of dual-gate OTFT has changed systematically with the application of voltage bias to top-gate electrode. When voltage bias from −10 V to 10 V is applied to top gate, V_th changes from 1.95 V to −9.8 V. Two novel types of the zero drive load logic inverter with dual-gate structure have been proposed and fabricated using PEALD Al₂O₃ gate dielectrics. Because the variation of V_th due to chemical degradation and the spatial variation of V_th are inherent in OTFTs, the compensation technology by dual-gate structure can be essential to OTFT applications.     

Field- and current-driven degradation of GaN-based power HEMTs with p-GaN gate: Dependence on Mg-doping level

Within this paper we investigate the degradation of GaN-HEMTs with p-GaN gate submitted to stress at forward gate bias. We studied the effect of both constant-voltage stress and short-pulse stress (induced by TLP, Transmission Line Pulser); devices having three different Mg-doping levels (ranging from 2.1 · 10¹⁹/cm³ to 2.9 · 10¹⁹/cm³) were used for the study.We demonstrated the existence of two different degradation mechanisms, depending on the stress conditions: (i) when submitted to TLP stress (100 ns pulses with increasing amplitude), the failure occurs through a field-driven process, i.e. the breakdown of the metal/p-GaN Schottky junction, which is reversely biased when the gate is at positive voltage. Failure voltage decreases with increasing Mg doping, since higher acceptor levels result in a higher electric field. (ii) Conversely, during constant-voltage stress, the long-term stability is undermined by a current-driven process, namely the accumulation of positive charges at the p-GaN/AlGaN interface, which promotes an increase of the leakage current, first gradual and then catastrophic. Increasing Mg-concentration in the p-GaN results in a reduction of the gate leakage at high forward gate bias. As a consequence, devices with higher Mg doping have long TTF (more than two orders of magnitude with respect to the samples with lower Mg doping).     

Strain sensitivity of gate leakage in strained-SOI nMOSFETs: A benefit for the performance trade-off and a novel way to extract the strain-induced band offset

The impact of biaxial stress on gate leakage is investigated on fully-depleted silicon-on-insulator (FD-SOI) nMOS transistors, integrating either a standard gate stack or an advanced high-κ/metal gate stack. It is demonstrated that strained devices exhibit significantly reduced leakage currents (up to ?90% at E_ox = 11 MV/cm for σ_tensile = 2.5 GPa). This specific effect is used to extract the conduction band offset ΔEc induced by strain and is shown to be accurate enough to monitor stress in MOSFETs. This new technique is much less sensitive to gate oxide defects than the method based on the threshold voltage shift ΔV_T. This accurate experimental extraction allowed us to pick out realistic values for the deformation potentials in silicon (Ξ_u = 8.5 eV and Ξ_d = ?5.2 eV), among the published values.     

All solution-processed organic single-crystal transistors with high mobility and low-voltage operation

High-mobility organic single-crystal field-effect transistors of 3,11-didecyldinaphtho[2,3-d:2′,3′-d′]benzo[1,2-b:4,5-b′]-dithiophene (C₁₀-DNBDT) operating at low driving voltage are fabricated by an all-solution process. A field-effect mobility as high as 6.9 cm²/V s is achieved at a driving voltage below 5 V, a voltage as low as in battery-operated devices, for example. A low density of trap states is realized at the surface of the solution-processed organic single-crystal films, so that the typical subthreshold swing is less than 0.4 V/decade even on a reasonably thick amorphous polymer gate dielectrics with reliable insulation. The high carrier mobility and low interface trap density at the surface of the C₁₀-DNBDT crystals are both responsible for the development of the high-performance all-solution processed transistors.     

Solution-processed single-crystalline organic transistors on patterned ultrathin gate insulators

Single-crystalline organic transistors of 3,11-didecyl-dinaphtho[2,3-d:2′,3′-d′]benzo[1,2-b:4,5-b′]dithiophene (C₁₀-DNBDT-NW) and 2,9-didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C₁₀-DNTT) were fabricated by solution processes on top of the patterned hybrid ultrathin gate dielectrics consisting of 3.6 nm-thick aluminum oxide and self-assembled monolayers (SAMs). Due to the excellent crystallinity of the channel films, bottom-gate and top-contact field-effect transistors exhibited the average field-effect mobility of 3.7 cm²/V s and 4.3 cm²/V s for C₁₀-DNBDT-NW and C₁₀-DNTT, respectively. These are the first successful devices of solution-processed single-crystalline transistors on ultrathin gate dielectrics with the mobility above 1 cm²/V s, opening the way to develop low-power-consumption and high-performance printed circuits.     

Realization of electrically stable organic field-effect transistors using simple polymer blended dielectrics

Organic field-effect transistors (OFETs) were fabricated using polymer blended gate dielectrics in an effort to enhance the electrical stability against a gate bias stress. A poly(melamine-co-formaldehyde) acrylated (PMFA) gate dielectric layer with great insulating properties was blended with polypentafluorostyrene (PFS), a type of hydrophobic fluorinated polymer. Although the overall electrical performance dropped slightly due to the rough and hydrophobic surfaces of the blend films, at the blend ratio (10%), the OFET’s threshold voltage shift under a sustained gate bias stress applied over 3 h decreased remarkably compared with an OFET based on a PMFA dielectric alone. This behavior was attributed to the presence of the hydrophobic and electrically stable PFS polymer, which provided a low interfacial trap density between the gate dielectric and the semiconductor. A stretched exponential function model suggested that the energetic barrier to create trap states was high, and the distribution of energetic barrier heights was narrow in devices prepared with PFS.     

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN_x/SiO₂ gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN_x/SiO₂) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (ΔV_TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.     

Non-functionalized soluble diketopyrrolopyrrole: Simplest p-channel core for organic field-effect transistors

We report the synthesis, characterization and behavior in field-effect transistors of non-functionalized soluble diketopyrrolopyrrole (DPP) core with only a solubilizing alkyl chain (i.e. –C₁₆H₃₃ or –C₁₈H₃₇) as the simplest p-channel semiconductor. The characteristics were evaluated by UV–vis and fluorescence spectroscopy, X-ray diffraction, cyclic voltammetry (CV), thermal analysis, atomic force microscopy (AFM) and density functional theory (DFT) calculation. For top-contact field-effect transistors, two types of active layers were prepared either by a solution process (as a 1D-microwire) or thermal vacuum deposition (as a thin-film) on a cross-linked poly(4-vinylphenol) gate dielectric. All the devices showed typical p-channel behavior with dominant hole transports. The device made with 1D-microwiress of DPP-R18 showed field-effect mobility in the saturation region of 1.42 × 10^?2 cm²/V s with I_ON/I_OFF of 1.82 × 10³. These findings suggest that the non-functionalized soluble DPP core itself without any further functionalization could also be used as a p-channel semiconductor for low-cost organic electronic devices.     

Experimental study for high effective mobility with directly deposited HfO2/La2O3 MOSFET

We experimentally examine the effective mobility in nMOSFETs with La₂O₃ gate dielectrics without SiO_x-based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N_s = 5 × 10¹¹ cm^?2 in the low 10¹¹ cm^?2 eV^?1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT.     

Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO₂-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node.     

Light-emitting field-effect transistors with π-conjugated liquid crystalline polymer driven by AC-gate voltages

Light-emitting field-effect transistors with a liquid crystalline polymer of poly[(9,9-dioctylfluorenyl-2,7-diyl)-co-bithiophene] (F8T2) were investigated under alternating current (AC) gate operations. Bottom-contact/top-gate devices were fabricated with indium-tin-oxide (ITO) source/drain electrodes, a poly(methyl methacrylate) dielectric and a gold gate electrode. The crystalline F8T2 film exhibited ambipolar characteristics with electron and hole mobilities of 1.8 × 10^?3 and 2.5 × 10^?3 cm²/V s, respectively, although the threshold voltage was considerably higher for electron injection. By applying square-wave voltages to the gate, light emission was obtained at the both edges of the source and drain electrodes by alternating injection of opposite carriers even when the source and drain were grounded. The light intensity was enhanced in the channel region by biasing the source negative while biasing the drain positive where the holes injected from the drain were transported to recombine with the electrons injected at the source edge.     

Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

CCD image sensor with compensated reset operation

A low voltage charge coupled device (CCD) image sensor has been developed by adjusting the electron potential barrier in the electron sensing structure. A charge injection to the gate dielectrics of a MOS transistor was utilized to optimize the electron potential level in the output structure. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 V to 5.5 V, which is suitable for compensating the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole–Frenkel conduction and Fowler–Nordheim conduction. A CCD image sensor with 492(H) × 510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200 °C). The devices annealing for 4 h at 200 °C exhibit good electrical properties with saturation mobility of 8.2 cm²V^?1s^?1, subthreshold swing of 1.0 V/dec and on/off current ratio of 5×10⁶. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20 V for 5000 s, the device annealing for 1 h shows a larger positive V_th shift of 4.7 V. However, the device annealing for 4 h exhibits a much smaller V_th shift of 0.04 V and more stable.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.