Lifetime prediction modeling of non-insulated TO-220AB packages with lead-based solder joints during power cycling

In this paper, a physical model is proposed to estimate the TRIAC solder joint fatigue during power cycling. The lifetime prediction is based on the following assumptions: the case temperature swing (ΔT_case) is the main acceleration factor, the solder joints are the weakest materials in the non-insulated TO-220AB TRIAC package and the plastic strain within the solder layer due to shearing is the failure cause.     

Real-time imaging of temperature distribution inside a power device under a power cycling test

The analysis of temperature distribution in a power device package is essential to increase the reliability of power devices, because the temperature swing during the operation creates mechanical stress at the interfaces between these materials. However, the temperature distribution is difficult to obtain under operating conditions because of the limitation in the use of non-destructive methods to measure the inside temperature of the device. In this paper, we propose a method of real-time imaging of temperature distribution inside a DUT. This method is based on a “real-time simulation”. The real-time simulation was realized by combining surface temperature monitoring and high-speed thermal simulation. The thermal simulator calculates temperature distribution inside the package by using the monitored surface temperature as a parameter. We demonstrate our system with a TO-220 package device under a power cycling test. The system indicated a temperature distribution change in the package with a frame rate of less than 1 s and the temperature difference at the Si chip was within 2 °C by a comparison with that estimated from forward voltage drop.     

Advanced power cycler with intelligent monitoring strategy of IGBT module under test

Power cycling (PC) test is one of the important test methods to assess the reliability performance of power device modules related to packaging technology, in respect to temperature stress. In this paper, an advanced power cycler with a real-time V_{CE_ON} and V_F measurement circuit for the IGBT and diode, which for the wear-out condition monitoring are presented. This advanced power cycler allows to perform power cycling test cost-effectively under conditions close to real power converter applications. In addition, an intelligent monitoring strategy for the separation of package-related wear-out failure mechanisms has been proposed. By means of the proposed method, the wear-out failure mechanisms of an IGBT module can be separated without any additional efforts during the power cycling tests. The validity and effectiveness of the proposed monitoring strategy are also verified by experiments.     

Power cycling issues and challenges of SiC-MOSFET power modules in high temperature conditions

Silicon carbide (SiC) MOSFETs power modules are very attractive devices and are already available in the market. Nevertheless, despite technological progress, reliability remains an issue and reliability tests must be conducted to introduce more widely these devices into power systems. Because of trapping/de-trapping phenomena at the SiC/SiO₂ interface that lead to the shift of threshold voltage, test protocols based on silicon components cannot be used as is, especially in high temperature conditions. Using high temperature SiC MOSFET power modules, we highlight the main experimental difficulties to perform power cycling tests. These reversible physical mechanisms preclude the use of temperature sensitive parameters (TSEP) for junction temperature measurements, so we set up fiber optic temperature sensors for this purpose. Moreover, these degradation phenomena lead to difficulties in both controlling the test conditions and seeking for reliable aging indicator parameters. Finally, a power cycling test protocol at high temperature conditions is proposed for such devices.     

Interface reliability and lifetime prediction of heavy aluminum wire bonds

In this study a high frequency mechanical fatigue testing procedure for evaluation of interfacial reliability of heavy wire bonds in power semiconductors is presented. A displacement controlled mechanical shear testing set-up working at a variable frequency of a few Hertz up to 10 kHz is used to assess the interfacial fatigue resistance of heavy Al wire bond in IGBT devices. In addition, power cyclic tests were conducted on IGBT modules for in-situ measurement of the temperature distribution in the devices and determination of the thermally induced displacements in the wire bond loops. Finite Element Analysis was conducted to calculate the correlation between the thermally and mechanically induced interfacial stresses in the wire bonds. These stress values were converted into equivalent junction temperature swings (ΔT_j) in the devices based on which lifetime curves at different testing frequencies were obtained. Comparison of the fatigue life curves obtained at mechanical testing frequencies of up to 200 Hz with the power cycling data related to the wire bond lift-off failure revealed a very good conformity in the ranges of 50 to 160 K. A lifetime prediction model for Al wire bonds in IGBT modules is suggested by which the loading cycles to failure can be obtained as a function of ΔT_j and the mechanical testing frequency. The proposed accelerated shear fatigue testing procedure can be applied for rapid assessment of a variety of interconnects with different geometries and material combinations. Decoupling of the concurrent failure mechanisms and separation of the thermal, mechanical and environmental stress factors allows a more focused and efficient investigation of the interfaces in the devices.     

Efficiency of gate control in double-interdigitated (TIL) GTO thyristors

The research reported in this work was focused on the efficiency of gate control during turn-off in the recently developed double-interdigitated (TIL) GTO thyristors. The 8 mm² area, TO-220 packaged, high voltage test devices were investigated under both current and voltage input conditions. The main monitored parameters were: the peak turn-off gain K_off(max), the components of the turn-off time and the gate pulse width t_gr. During the tests the TIL GTOs were driven up to an anode current i_T = 50 A, a value equal to the non-repetitive peak on-state current (I_TSM) of these thyristors.The performed investigations have shown that these novel GTO devices possess a good efficiency of gate control expressed by: 1) low power consumption by the gate under both current and voltage drive conditions; 2) extremely high turn-off gain K_off(max), which is an increasing function of the anode current in a wide range of gate signals amplitudes and durations; 3) fast turn-off of large amounts of anode current with relatively short gate pulse widths; 4) substantial reduction of the storage time t_s and fall time t_f through adequate current or voltage drive. Design/behavioral details are given, which are useful in the implementation of the TIL concept in GTOs and other power switching devices, such as the bipolar transistors.     

绝缘引线在陶瓷封装中的应用

随着半导体封装持续朝着多引脚、小节距及多列多层叠的方向发展,引线键合技术正面临越来越大的挑战。当陶瓷空封器件中的键合引线长度大于3.0 mm时,在加电冲击试验过程中键合引线容易出现瞬间的短路而导致器件失效。文章主要阐述了产生该问题的基本原因,提出了采用绝缘引线键合解决该问题的可行性,介绍了绝缘引线的基本特性,并用实际封装的电路进行了绝缘引线键合的可靠性研究,根据研究结果,提出了绝缘引线可有限应用于陶瓷封装的结论。     

基于ANSYS的功率VDMOS器件的热分析及优化设计

针对TO-220 AB封装形式的功率VDMOS器件,运用有限元法建立器件的三维模型,对功率耗散条件下器件的温度场进行热学模拟和分析,研究了基板厚度、粘结层材料及粘结层厚度对器件温度分布的影响.分析结果表明,由芯片至基板的热通路是器件的主要散热途径.基板最佳厚度介于1～1.2 mm之间,且枯结层的导热系数越大、厚度越薄,越有利于器件的散热.     

High temperature long term stability of SiC Schottky diodes

Reliability of Silicon Carbide (SiC) power devices is still an open problem, preventing a wider application of such a promising technology. Moreover, specific reliability assessment procedures must be developed for SiC devices, as they are designed to work at temperatures well beyond those of standard Silicon devices. A detailed investigation about the reliability of 600 V, 6 A Silicon Carbide Schottky diodes is accomplished along this paper. It is based on an extensive set of high temperature reverse bias endurance tests, performed on devices featuring different packages. Only small forward voltage drop and reverse current drifts have been recorded after a 1000 h long test, confirming the parametric stability and the reliability level reached by last generation SiC Schottky diodes. Moreover, devices assembled in TO220 package without flame retardant components in the molding compound performed better than devices assembled in other TO220 packages, or assembled in hermetic TO3 package, pointing out the role played by the interface between the green molding compound and the top passivation layer in the long term parametric stability.     

Material properties of anisotropic conductive films (ACFs) and their flip chip assembly reliability in NAND flash memory applications

In this paper, the material properties of anisotropic conductive films (ACFs) and ACF flip chip assembly reliability for a NAND flash memory application were investigated. Measurements were taken on the curing behaviors, the coefficient of thermal expansion (CTE), the modulus, the glass transition temperature (T_g), and the die adhesion strength of six types of ACF. Furthermore, the bonding processes of the ACFs were optimized. After the ACF flip chip assemblies were fabricated with optimized bonding processes, reliability tests were then carried out. In the pressure cooker test, the ACF with the highest adhesion strength showed the best reliability and the ACF flip chip assembly revealed no delamination at the chip-ACF interface, even after 96 h. In the high temperature storage test and the thermal cycling test, the reliability of the ACF flip chip assembly strongly depends on the T_g value of the ACF. In the thermal cycling test, in particular, which gives ACF flip chip assemblies repetitive shear stress, high value of CTE above T_g accelerates the failure rate of the ACF flip chip assembly. From the reliability test results, ACFs with a high T_g and a low CTE are preferable for enhancing the thermal and thermo-mechanical reliability. In addition, a new double-sided chip package with a thickness of 570 μm was demonstrated for NAND flash memory application. In conclusion, this study verifies the ACF feasibility, and recommends the optimum ACF material properties, for NAND flash memory application.     

A fast mechanical test technique for life time estimation of micro-joints

A novel accelerated mechanical testing method for reliability assessment of micro-joints in the electronic devices is presented as an alternative to time consuming thermal and power cycling test procedures. A special experimental set-up in combination with an ultrasonic resonance fatigue testing system and a laser Doppler vibrometer is used to obtain fatigue life curves of micro-joints under shear loading. Using this method fatigue life curves of Al wire bonded micro-joints were obtained up to 10⁹ number of loading cycles and discussed with regard to micro-mechanisms of the bond failure. Failure analysis of the fatigued micro-joints showed that the predominant failure mechanism of power cycling tests, bond wire lift-off, was reproduced by the mechanical testing procedure. Life time of the micro-joints was modelled using a Coffin–Manson type relationship and showed a good correlation to life time curves obtained by power cycling tests. The major advantage of the proposed fast mechanical testing method is the significant reduction of the testing time in comparison with conventional thermal and power cycling tests. Furthermore subsequent examination of the failure surface provides a reliable tool for improvement of the bonding process. The proposed high frequency fatigue testing system can be applied as a rapid qualification and screening tool for various kinds of interconnects in electronic packaging.     

Increasing the current-handling capability of TIL GTO thyristors up to its limits—II. Experimental

The theoretical analysis and the developed design criteria for TIL GTO thyristors presented in the first part of this study (Paper I) are validated experimentally. The TO-220-packaged, high-voltage (V_DRM = V_RRM = 1000–1500 V) test TIL GTOs had a total cathode area of 8 mm², of which the area of deep-diffused cathode zones amounted to 3.5 mm². The implementation of optimized technological/geometrical ratios for TIL gate-cathode configuration yielded TIL GTO thyristors with a maximum controllable anode current of 55 A, which is the highest value of I_ATO reported thus far in the open literature for this class of GTOs (identical device area and case). All technological factors and physical effects underlying this achievement are analyzed in detail in this work. The current balancing between the two types of elementary p-n-p-n sections (standard and quasi-nonregenerative) constituting the vertical structure of the novel device is checked experimentally and the impact of this peculiar effect on current-handling capability of TIL GTOs is assessed both qualitatively and quantitatively. The boost of I_ATO up to its limits, ultimately dictated by the thermal impedance junction-to-case Z_thj?c TO-220-packages, was accompanied by a significant increase of the peak turn-off gain (10–20) of these devices at higher levels of anode current and by failure-safe operation of TIL GTOs at high commutation frequencies (up to hundreds of kHz) under heavy load conditions. The developed devices possess an excellent turn-on sensitivity and a high immunity to noise (high dV/dt capability). All the results of this work show clearly that sought-for benefits could be obtained by using the optimized double-interdigitated (TIL) gate-cathode pattern in GTO thyristors. The notation used is the same as in Paper I.     

Study of thermal cycling and temperature aging on PbSnAg die attach solder joints for high power modules

High power modules are still facing the challenges to increase their power output, increase the junction temperature, and increase their reliability in harsh conditions. Therefore this study is doing a detail analysis of the soldering joint between a direct copper bonded substrate and a high power IGBT made with the high lead solder alloy Pb_92.5Sn_5.0Ag_2.5. The intermetallic phases and the microstructure of standard chip to substrate solder joint will be analysed and compared to deteriorated joints coming from modules which have undergone an active thermal cycling. As expected, the as soldered joint was clearly different than solder joints made for ball grid array or small components on PCBs. The as soldered joint shows no sign of Cu₆Sn₅ intermetallic layer, but instead shows the presence of Ag₃Sn particles at the solder–chip interface. Furthermore, the failure mechanisms under active thermal cycling also seem to be different. There is no growth of intermetallic phases and no strong delamination of the device. Instead a large network of intermetallic particles (Ag₃Sn) is produced during aging and seems to degrade the solder thermal properties.     

Comparison of IGBT short-circuit failure “ohmic mode”: Epoxy molded package versus silicone gel module for new fail-safe and interruptible power converters

An epoxy molded package is compared with a silicone gel module with IGBTs chips in short-circuit failure modes with respect to critical energy, I²T_melting and explosion energy capabilities. Special importance was attached to “ohmic mode” assessment and ageing of the failed chips. The molded technology yields a very low and stable R_sc (<10 mΩ) as a “residual ohmic value” of the dies in low energy short-circuit failure, which is analysed through a complete reverse. Continuous thermal cycling tests over a medium time duration (>1000 h) also exhibit an acceptable drift of the R_sc property (<20%). The silicone gel module clearly exhibits an unstable R_sc value due to damage of the “free moving” wire-bonding on the chips. The authors show that the paralleled wires connections and the multiple parallel melting pits allow a sort of active redundancy and a possible on-state operation. All these results are used for the design of new and original failsafe converters. These topologies use only one paralleled safety leg that is spontaneously and directly connected in series with the failed devices, through the low R_sc value of the failed chips, without any additional complexity or extra cost.     

Fast power cycling protocols implemented in an automated test bench dedicated to IGBT module ageing

This paper presents fast test protocols for ageing IGBT modules in power cycling conditions, and a monitoring device that tracks the on-state voltage V_CE and junction temperature T_J of IGBTs during ageing test operations. This device is implemented in an ageing test bench described in previous papers, but which has since been modified to perform fast power cycling tests.The fast test protocols described here use the thermal variations imposed on IGBT modules by a test bench operating under Pulse Width Modulation conditions. This test bench reaches the maximal values of power cycling frequencies attainable with a given module packaging in order to optimize test duration.The measurement device monitors V_CE throughout the ageing test that is needed to detect possible degradations of wire bonds and/or emitter metallization. This requires identifying small V_CE variations (a few dozen mV). In addition, the thermal swing amplitude of power cycling must be adjusted to achieve a given ageing protocol. This requires measuring junction temperature evolution on a power cycle, which is carried out by means of V_CE measurement at a low current level (100 mA).Experimental results demonstrate the flexibility of this test bench with respect to various power cycling conditions, as well as the feasibility of the proposed on-line monitoring methods.     

Soft solder die bonding of multiple die devices

The aim of the work presented in this paper is to study the soft solder die attach of multiple die devices by a multiple pass process. With a multiple pass process we mean a procedure which needs as many die bonder furnace passes as there are different types of dice to be bonded into a package. The main focus of the investigation is on the effect of the necessary multiple furnace passes on the reliability of the soft solder attachment layer. As this behavior may depend on the specific type of device or package (i.e., solder alloy-substrate combination, die size, package geometry), it is analyzed relative to the one of an identical die processed in one single furnace pass. A real package (TO-220) is used as test vehicle and processed on standard equipment. A detailed analysis of the multiple pass process relative to a single pass process with appropriate equipment is performed. It is concluded that a multiple pass process may be slightly less efficient for throughput. However it gives more process flexibility and allows using standard equipment which is available on the market. The result of this investigation strongly supports the feasibility of multiple die devices with a multiple pass process. No reliability limiting influence of the additional furnace passes causing a repeated re-melting and re-solidifying of the solder layer is found. It is, however, necessary to investigate the capability for any other specific device or package again     

Reliability of Lead-Free Solder Interconnections in Thermal and Power Cycling Tests

Lead-free solder interconnection reliability of thin fine-pitch ball grid array (BGA) lead-free packages has been studied experimentally as well as with finite-element (FE) simulations. The reliability tests were composed of the thermal shock test, the local thermal cycling test (resistors embedded in the board around the package), and the power cycling test (heat generation in the die). A 3-D board-level finite-element analysis (FEA) with local models was carried out to estimate the reliability of the solder interconnections under various test conditions. Due to the transient nature of the local thermal cycling test and the power cycling test, a sequential thermal-structural coupling analysis was employed to simulate the transient temperature distribution as well as the mechanical responses. Darveaux's approach was used to predict the life time of the solder interconnections. Furthermore, the numerical results validated by the experimental results indicated that the diagonal solder interconnections beneath the die edge were the most critical ones of all the tests studied here. It has been found that the fatigue life in the power cycling test was much longer than that in the other two tests. Detailed discussions about the failure mechanism of solder interconnections as well as the microstructural observations of the primary cracks are reported in this paper.      

Reliability modeling of Sn–Ag transient liquid phase die-bonds for high-power SiC devices

In this work, a novel foil-based transient liquid phase bonding process has been used to mount the SiC Schottky diodes. The Sn–Ag TLP interlayer material was produced in the form of preforms of multilayer foils, using electrochemical deposition. The foils were designed to keep the overall composition of Ag and Sn about 80% and 20% respectively. The optimized TLP bonding process parameters were used during the assembly process. The die-attachment characterizations revealed that resulting intermetallic compounds (Ag₃Sn and ζ) have melting point beyond 480 °C. The die-attachment produced low bending stresses, while heated from 30 °C to 400 °C. The reliability of Sn–Ag TLP bonded samples was studied during passive temperature cycling and during active power cycling. During power cycling, the crack rates were determined by measuring the crack lengths of the TLP bonded joints after failure. The failure criteria were set to be an increase of diode's forward voltage by 10% since the start of the power cycling tests. The thermo-mechanical simulations were performed to determine the damage parameter i.e. strain range amplitude ∆ ε_p. Based on mechanical characterization of the TLP bonded layers, a plastic material model was used. The crack propagation rates were modeled using Paris' Law. Based on comparisons with state-of-the-art silver sintering technique, it can be stated that the TLP bonding is a promising die-attachment technique and its power cycling reliability is similar to silver sintering.     

Interface Microstructure and Performance of Sb Contacts in Bismuth Telluride-Based Thermoelectric Elements

A thermoelectric joint composed of p-type Bi_0.5Sb_1.5Te₃ (BiSbTe) material and an antimony (Sb) interlayer was fabricated by spark plasma sintering. The reliability of the thermoelectric joints was investigated using electron probe microanalysis for samples with different accelerated isothermal aging time. After aging for 30 days at 300°C in vacuum, the thickness of the diffusion layer at the BiSbTe/Sb interface was about 30 μm, and Sb₂Te₃ was identified to be the major interfacial compound by element analysis. The contact resistivity was 3 × 10^?6 ohm cm² before aging and increased to 8.5 × 10^?6 ohm cm² after aging for 30 days at 300°C, an increase associated with the thickness of the interfacial compound. This contact resistivity is very small compared with that of samples with solder alloys as the interlayer. In addition, we have also investigated the interface behavior of Sb layers integrated with n-type Bi₂Se_0.3Te_2.7 (BiSeTe) material, and obtained similar results as for the p-type semiconductor. The present study suggests that Sb may be useful as a new interlayer material for bismuth telluride-based power generation devices.     

Power gain and noise of InP and GaAs insulated gate microwave FETs

LPE GaAs and InP n-channel depletion mode insulated gate field effect transistors (MISFETs) having 4 μm gate lengths have been fabricated employing pyrolytic Si_xO_yN_z, pyrolytic SiO₂ and an anodic dielectric for gate insulation.The microwave power gain, noise figure, maximum output power and power-added efficiency were measured and compared to those parameters measured on GaAs Schottky barrier gate devices of identical geometry. The results show that, at least at the microwave frequencies measured, power gain and noise are essentially the same in the GaAs Schottky gate FET and anodic MISFET devices while the maximum output power of a typical InP MISFET was greater than that of a representative GaAs Schottky device.