CMOS宽动态范围的可变增益放大器

采用CMOS工艺,针对超外差结构的无线宽带接收器,提出了一个新结构的可变增益放大器,并对该放大器进行了仿真和测试.测试和仿真结果表明:该放大器能够工作在5 0～6 0 0MHz的频率上,增益为- 2 8～4 2dB ,最大增益的噪声系数为7 6 5dB ,最小增益的IIP3为2 0dBm ,而且具有良好的鲁棒性,在3V的电源电压下,电流消耗只有12mA .     

凌力尔特推出新的固定增益放大器

正2014年4月14日-凌力尔特公司(Linear Technology Corporation)推出20 MHz至2 GHz、单端输入及输出、固定增益放大器LTC6431-20,该器件提供卓越的46.2 dBm OIP3(输出三阶截取)和2.6 dB噪声指数。其OP1dB(输出1dB压缩点)为同类最佳的22 dBm。该器件有两个级别版本,包括100%经过测试、在240MHz保证提供42.2 dBm最低OIP3的A级版本,以及在同样的频率范围提供45.7 dBm典型OIP3的B级版本。该器件在20 MHz至1.4 GHz的频率范围内,输入和输出均在内部匹配至50 Ω,并具有一个20 dB功率增益     

新品发布

RF VGA提供增益和功率控制单片射频(RF)可变增益放大器或衰减器(VGA)能提供1MHz～3GHz宽频带具有以dB为单位呈线性60dB增益控制范围,集成了宽带放大器和衰减器,具有60dB动态增益和衰减范围(大约+20dB增益和-40dB衰减),22dBm输出功率水平(1dB压缩点),在1GHz频率和8dB噪声系数下具有+31dBm输出三阶截点。ADIhttp://www.analog.com具有超低抖动的时钟AD951x系列时钟分配芯片集成了低相位噪声的PLL频率合成器内核、可编程分频器和可调延迟单元电路。器件具有亚皮秒抖动的低相位噪声时钟输出,LVPECL时钟输出达800MHz,附加抖动小…     

CMOS宽动态范围的可变增益放大器

采用CMOS工艺,针对超外差结构的无线宽带接收器,提出了一个新结构的可变增益放大器,并对该放大器进行了仿真和测试.测试和仿真结果表明:该放大器能够工作在50～600MHz的频率上,增益为-28～42dB,最大增益的噪声系数为7.65dB,最小增益的IIP3为20dBm,而且具有良好的鲁棒性,在3V的电源电压下,电流消耗只有12mA.     

一种宽带接收射频前端设计与实现

本文设计了一种超外差架构的超宽带接收射频前端,工作频段覆盖400MHz~2000MHz,接收增益50dB,噪声系数小于6dB,中频输出频率70MHz,输出1dB压缩点大于18dBm,输出三阶交调节点大于30dBm,瞬时态范围大于55dB,测试结果和仿真结果基本一致,符合设计预期.     

用于77GHz毫米波雷达的模拟基带电路设计

实现了一个带宽和增益可配置、高线性度、低噪声的模拟基带电路,可应用于77 GHzCMOS毫米波雷达接收机.电路包括一个带宽可配置的5阶巴特沃斯低通滤波器模块、三个可编程增益放大器模块以及三个直流失调消除环路.增益范围为18～70 dB,增益步进为6 dB;带宽为200 kHz～2 MHz;噪声系数最小为24 dB;输出1-dB压缩点为5.1 dBm,在最高增益时,IIP3为-52dBm;功耗为14.6 mA@1 V.电路采用65 nm CMOS工艺实现,芯片面积为1.2×0.93 (mm2).     

高输出电压的宽带程控增益放大系统

设计了以电压控制可变增益放大器AD603为程控增益主体,以MSP430F449单片机为控制核心的高电压输出宽带程控增益放大系统.系统电压增益为0～60 dB可调,3 dB带宽2.5 MHz、5 MHz、10 MHz、15 MHz可调,最小输入电压有效值为1 mV,在50 Ω负载下最大不失真输出电压峰峰值为28 V,电压...     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

一种3～5 GHz连续增益可调CMOS超宽带LNA的设计

提出了一种具有大范围连续增益变化的3～5 GHz CMOS可调增益低噪声放大器.采用两级共源共栅电路结构,二阶切比雪夫滤波器作为输入,源跟随器作为输出,在带内获得了良好的输入输出匹配和噪声性能.通过控制第二级的偏置电流,获得了36 dB的连续增益可调,同时也不影响输入输出匹配.该电路基于TSMC 0.18 μm CMOS工艺,在最高增益时,输入和输出反射系数S11和S22分别小于-10.1 dB 和-15 dB,最高增益达到23.8 dB,最小噪声系数仅为1.5 dB,三阶交调截点为-7 dBm,在1.2 V电压下,功耗为6.8 mW;芯片面积0.71 mm2(0.96 mm×0.74 mm).     

用于WiMAX的高线性度1W和2W放大器

可以支持750MHz～3．9GHz频带,ALM～31X22功率放大器内置有源偏压电路并且不需射频匹配器件。在典型的5V和400mA偏压条件下,ALM-31122可以在900MHz下带来31．6dBm输出功率（P1dB）、47．6dBm的OIP3和15.6dB增益。ALM-31222则可以在2GHz时提供31．5dBmP1dB、47．9dBm OIP3和14．9dB增益的输出。     

A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers

A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and /spl Sigma//spl Delta/ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order /spl Sigma//spl Delta/ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass /spl Sigma//spl Delta/ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW.     

雷达中频放大器的线性对数双特性设计

雷达数字中频接收机需要一个线性中频预放大电路和一个监测用的对数中频放大器。采用射频变压器形成输入匹配网络,采用高性能低噪声宽带差分放大器AD8350作为线性放大器件,采用双调谐回路作为选频网络,采用魔T电路构成功率分配网络,采用高动态范围宽带对数放大器AD8309作为对数放大器件,设计了一个兼具线性和对数特性的中频放大器。实验表明,该放大器中频输入输出阻抗50Ω,中心频率30 MHz,带宽4 MHz。线性通道增益为18 dB,输出动态范围达98 dB(1 dB压缩点-90 dBm和+8 dBm)。对数通道中,在输入功率为-68 dBm～-8 dBm时,对数放大器输出电压范围对应为0.19 V～2.06 V。     

A polar modulator transmitter for GSM/EDGE

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.     

A high-IP3 RF receiver chip set for mobile radio base stations upto 2 GHz

We present a monolithically integrated high third-order intercept point (IP3) radio frequency (RF) receiver chip set for mobile radio base stations up to 2 GHz, in a 25-GHz f_T Si bipolar production technology. The chip set consists of a RF preamplifier, active mixer circuits, and an intermediate frequency (IF) limiter. The preamplifier gain is 12 dB, the noise figure is 5.5 dB at 900 MHz, and the output (OIP3) is up to +24 dBm depending on supply voltage. The two different mixers provide a conversion gain of 1.5 dB up to 3 dB, an OIP3 in the range of +21 dBm up to +29 dBm, and a minimal single sideband (SSB) noise figure of 13 dB. The IF limiter shows an excellent limiting characteristic at 10 dBm output power and has a high bandwidth of more than 1 GHz     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

用于卫星双向时间传递系统的调制器设计

设计开发了一种用于卫星双向时间传递(TWSTT) 系统的调制器,详细介绍了该调制器 的内部结构和相关算法。采用FPGA和DDS进行硬件实现,并完成系统的仿真测试。该调制器 的中频输出频率为70 MHz,峰值输出功率为-15 dBm。     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A variable gain amplifier with 50-dB control range for 900-MHz applications

A variable gain amplifier for 900-MHz applications has been designed and fabricated in a BiCMOS process with f/sub T/ = 24 GHz. The amplifier has linear-in-dB gain control with a 50-dB control range. The maximum gain is 28 dB and the third-order output intercept point (OIP3) is 13.7 dBm. The gain is achieved in one gain stage with a cascoded output. The amplifier bias network and the gain-control circuitry are temperature compensated for temperature-independent gain at any gain setting. The bias network also uses a feedback loop to cancel out undesired low frequencies present at the radio-frequency input. The maximum output power is +10 dBm and the output 1-dB compression point is +8.7 dBm. Active chip area is 0.1 mm/sup 2/. The amplifier is packaged in a SOT-363 and consumes 30 mA from a 2.8-V supply.     

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.     

Prediction of Wide-Band Power Performance of MESFET Distributed Amplifiers Using the Volterra Series Representation

The power performance of a four-section MESFET distributed amplifier is predicted over the frequency range 2-8 GHz. The nonlinear model of the MESFET used has three nonlinear elements: g/sub d/, and C/sub gs/, which are represented by power series up to the third order. The analysis employs the Volterra series representation up to the third order. Experimental verification is first made on a 0.5x400-µm medium-power MESFET device to confirm the validity of the nonlinear model used in the analysis. The agreement between predicted and measured output power at 1-dB gain compression is within +-0.5 dBm across the 2-16 GHz band. A four-section distributed amplifier was then built with four 0.5x400-µm MESFET's. The agreement between predicted and measured output power at 1-dB gain compression of this amplifier is within +-0.7 dBm across the 2-8-GHz band. The measured output power at 1-dB gain compression is (22+-1) dBm across the 2-8-GHz band.