PDP能量恢复电路硬开关问题的研究

等离子显示器在没有能量恢复电路的情况下,功耗很大,不能广泛实用,因此能量恢复电路是驱动电路中至关重要的部分.能量恢复电路中的高压开关MOSFET的硬开关问题,会导致PDP电路中的较大的放电电流,增大电磁干扰(EMI),影响整机性能.硬开关问题是近年来PDP电路研究的重点之一.本文通过对经典能量恢复电路及其寄生效应进行理论分析,指出电路及其元件中的寄生效应是电路中主要MOSFET产生硬开关问题的主要原因,由此分析了研究了改进这一问题的几种方法.     

PDP扫描电极高压驱动电路的研究

介绍了PDP驱动电路的构成,在分析扫描电极高压驱动波形和驱动电路设计考虑的基础上,研究了扫描电极高压驱动电路的实现方法,并对能量恢复电路作了一定的介绍。通过电路分析,该驱动电路能够完成各个时期输出相应脉冲的要求,且能量恢复电路能够降低系统功耗。     

一种新型的AC-PDP能量恢复电路

在简单介绍表面放电型AC-PDP的结构和发光原理的基础上,引出能量恢复电路的思想.介绍常用的能量恢复电路及其工作过程,指出该类电路的弊端.提出一种全新的能量恢复电路,最后给出了其控制波形.     

PDP驱动芯片用能量恢复电路的设计

主要提出了一种基于PDP驱动芯片的能量恢复电路,该电路利用将各个输出端通过控制高压开关管连接在一起进行电荷共享的原理,经过Hspice仿真验证具有完整的功能,并在CSMC0.5μm CMOS工艺下得到实现.仿真结果表明这种能量恢复电路不仅可以显著降低驱动芯片的能量损耗,并且具有结构简单的特点,目前被应用于一款等离子电视的列驱动芯片中,降低芯片功耗,提高芯片工作的稳定性.     

超高频无源射频标签的射频接口设计

对射频标签能量供应原理进行了详细的理论分析,设计了一个超高频远距离无源射频标签芯片的射频接口电路,包括电源恢复电路、稳压电路及解调整形电路。解决了超高频无源射频标签远距离能量供应和信号获取的问题。射频接口电路采用UMC 0.18μm混合信号工艺流片验证。测试结果表明,射频接口电路的性能可满足超高频远距离无源射频标签芯片的要求。     

交流PDP驱动线路中的能量恢复电路

本文针对目前交流ＰＤＰ驱动电路所普遍采用的能量恢复电路,就其工作原理作以简要介绍。该电路可在很大程度上减少ＰＤＰ驱动方式本身所造成的不必要的能量损耗。     

部分谐振式PDP能量恢复电路的研究

介绍了等离子平板显示器(PDP)的驱动原理,引入了一种新型部分谐振式能量恢复电路,此电路利用谐振原理使扫描驱动IC的工作电压比常规方法有明显降低,能量恢复效果明显,实验证明其可以大大减少PDP能量损耗,提高系统性能,具有广泛的应用前景.     

一种宽频的数据时钟自恢复电路的设计

介绍了一种加宽数据时钟自恢复电路的可恢复时钟频率带宽的方法，重点提出了时钟锁定的检测电路及时钟输出的选择电路的设计，并进行了分析。     

一种上变频自供电无线传感器电源管理电路

电线周围的电磁场能量密度低,电磁换能器采集到的能量通常无法直接驱动无线传感器正常工作.论文采用上变频技术,设计了一种自供电电源管理电路来提高能量采集效率.由于电路的输出功率与品质因数成正比,且品质因数的大小与电路谐振电容的根号值成反比,因此通过提高电路的工作频率来减小谐振电容值,可以使高品质因数的电路产生更高的输出功率,进而增加能量采集效率.实验结果表明,该电路的最大能量采集效率是传统桥式整流电路的2.1倍.当电线中通过1A、50Hz的交流电时,电源管理电路最大采集功率为780μW,能量采集效率达到48.75%.当管理电路中超级电容能量积累达到一定程度,电容放电驱动无线传感器工作.     

胶囊内窥镜中高效全向能量接收芯片的设计

能量接收电路最主要的性能参数为功率转换率。为了提高电压转换率和功率转换率,通过对全向能量接收电路的理论分析,提出了使用低功耗高速比较器来控制mos管开关的方法。同时分析了闩锁效应,采用CMOS工艺设计了一种应用于胶囊内窥镜的高效全向能量接收电路。并用CSMC 0.5um工艺对该电路进行了仿真,仿真结果表明,该电路的电压转换效率可达97%,满足内窥镜对能量的要求。     

New Gate-Bias Voltage-Generating Technique With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process

A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-mum LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

Single-bit digital comparator circuit design using quantum-dot cellular automata nanotechnology

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.     

一种基于低温多晶硅薄膜晶体管的交流AMOLED像素补偿电路

This paper presents a new poly-Si pixel circuit employing AC driving mode for active matrix organic light-emitting diode （AMOLED） displays. The proposed pixel circuit, which consists of one driving thin-film tran- sistor （TFT）, three switching TFTs, and one storage capacitor, can effectively compensate for the threshold voltage variation in poly-Si and the OLED degradation. As there is no light emission, except for during the emitting period, and a small number of devices used in the proposed pixel circuit, a high contrast ratio and a high pixel aperture ratio can be easily achieved. Simulation results by SMART-SPICE software show that the non-uniformity of the OLED current for the proposed pixel circuit is significantly decreased （〈 10%） with an average value of 2.63%, while that of the conventional 2T1C is 103%. Thus the brightness uniformity of AMOLED displays can be improved by using the proposed pixel circuit.     

Even Order Harmonic Series-L/Parallel-Tuned Class-E Frequency Multiplier

In this brief, we propose a new class-E frequency multiplier based on the recently introduced series-L/parallel-tuned class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.     

High injection efficiency readout circuit for low resistanceinfra-red detector

A new input circuit, called the current mirroring direct injection (CMDI) circuit, is proposed for infra-red detector readouts. This new input circuit leads to almost 100% injection efficiency even in the case of low diode dynamic resistance. In addition, it can provide a stable detector bias and can be implemented with a small unit cell area and low power consumption     

TFT-LCD驱动芯片的二级驱动电路

针对单芯片集成的TFT-LCD驱动芯片的特性,提出了在γ校正电路中加入两级驱动Buffef的驱动电路结构,以及提高其驱动能力的有效措施.对于具有13个驱动buffer的二级驱动电路,当由一个灰度电压驱动全部396个像素单元时,驱动电压的最大安定时间约为19.2μs;静态消耗电流为518μA,与传统的64个驱动buffer电路相比,其功耗减小了77%.本文的设计结果已成功应用于132RGB×176分辨率、26万色彩色显示手机用TFT-LCD驱动芯片中,其也可用于PDA、数码相机等其他便携电子设备的显示驱动.     

Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.     

一种基于伪LRU的新型共享Cache划分机制

本文提出了一种基于伪LRU方法的新型共享Cache动态划分策略PLRU-SCP.本文提出的划分策略在分析电路中给出了基于二叉树的新型分析方法,在划分电路中使用了一种非遍历的划分算法.并提出了一种新型共享Cache结构.本文提出的新型划分策略比基于LRU方法的不划分共享Cache策略和效用最优的划分策略的性能分别提高了11.05%和8.66%.     

Slew rate enhancement method for folded-cascode amplifiers

A new circuit is proposed to enhance the slew rate (SR) of the folded-cascode amplifier (FCA). The proposed circuit is automatically activated during the slewing phase. Simulation results show a fourtimes improvement in the SR and close to 40% reduction in the settling time, compared to a conventional FCA