单片机和可编程逻辑器件通用接口设计及应用

在研制基于单片机的智能仪器“导爆索、雷管爆速校准仪”的过程中,引入可编程逻辑器件来处理超过单片机处理能力范围的高速信号,并开发了一套有效结合单片机和可编程逻辑器件的方法。     

车辆电子标识及识别系统通用技术探讨

本文针对我国车辆电子标识及识别系统标准技术体系,从技术体系,识别设备分类、功能要求、安全要求、可靠性等方面进行了分析和研究,为车辆电子标识系列标准制定提供技术支持和帮助。     

电子元器件标准的军民通用研究

针对电子元器件标准的军、民通用提出了"单元组合"和"等级划分"两种实现标准军民通用的理论方法.就电子元器件标准军民通用的几个关键问题进行了研究,认为电子元器件标准的军民通用有扩大趋势,但电子元器件标准的军民通用是有限通用,不同类型的标准可以实现军民通用化的程度明显不同,因此应采取不同策略.推动电子元器件标准军民通用必须是军方主导,且应循序渐进.含铅与否及含铅量的规定是电子元器件标准军民通用过程中需要考虑的一个重要技术问题.     

采用VXI总线系统实现通用仪器自动校准的方法研究

本主要介绍了采用VXI总线的通用仪器综合校准系统,讨论了在实现参数自动校准过程中的校准方法,解决了采样法测量失真、检波法测量高频电压和间接法测量单线时间间隔等技术难题。     

探析计算机通用技术的应用

随着信息时代的到来,计算机技术的飞速发展,计算机在各行业各部门内的运用也逐渐频繁并深人,在医学、教育、工程等很多领域都有涉及,计算机通用技术得到了很大的普及和发展,提高了城市的工作效率。本文简单分析并研究了计算机通用技术的应用价值．     

符合SMBIOS规范的通用采集接口的实现

对于桌面级的数据采集方法大多采用Windows API和访问注册表来实现,但其却不能对BIOS进行很好的管理,尤其对SMBIOS规范中的附加数据收集功能和精确系统识别功能缺乏支持,本文将利用EPS表对SMBIOS版本进行识别,并采用WMI(Windows管理规范)实现SMBIOS数据的采集通用接口的设计。     

IEEE—488通用接口的控制及应用

本文讨论如何将PC机开发成GPIB主控机的方法,为PC机的488接口设计了功能强、调用方便的接口控制软件,某些语句达到了语言扩充式主控机的效果,大大方便了自动测试程序的设计。该软件已成功地应用在我们的高温自动检定系统中,取得了良好的效果。     

通用卡尺多功能专用检具的研制与应用

利用量块具有一对相互平行测量面且量块的测量面可以和另一量块的测量面相研合而组合使用的特性,研制了可对通用卡尺内外尺寸等进行检定或校准的专用夹具。阐述使用通用卡尺多功能专用检具对卡尺内外尺寸等进行检定的特点。从而解决了检定通用卡尺当前无专用内尺寸检具的难题。     

桥梁通用现场监测软件系统设计及应用

针对特定桥梁开发的现场监测软件系统通用性较差，不能满足不同类型桥梁现场监测的要求。在充分分析桥梁现场监测软件通用性要求的基础上，设计了一种基于数据库的桥梁通用现场监测软件。采用配置数据库和动态链接库形式实现了桥梁现场监测的各种通用性要求。该软件在Delphi开发平台下实现，采用了SQL Server数据库管理系统。实践证明，该软件稳定可靠，适用于不同桥梁的现场监测。     

GPRS无线应用的通用平台设计

在实际的生产中,开发一个GPRS无线应用平台往往是针对具体的对象来采用专用的设计方案:设计用户应用模块、设计GPRSDTU(Data Terminal Unit数据终端单元)、设计服务器应用程序等。本文提出了一种常规平台结构,在外围提供通用的通讯接口,用户能够根据自己的实际应用在此平台上面进行二次开发,降低了开发的成本和难度,缩短了开发的时间。     

A Novel Design of Octal-Valued Logic Full Adder Using Light Color State Model

Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner, the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area. This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing. We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model. Four case studies were used to assure the validity of the proposed adder. These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.     

Construction of a Fuzzy and Boolean Logic Gates Based on DNA

Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA‐based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA‐based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three‐dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics.     

改进的AlGaN/GaN HEMT小信号参数提取算法

制作了截止频率ft和最高震荡频率fmax分别为46.2和107.8 GHz的AlGaN/GaN高电子迁移率晶体管,并针对该器件建立了包含微分电阻Rfd和Rfs在内的18元件小信号等效电路模型;在传统的冷场条件提取器件寄生参数的基础上,通过对不同栅压偏置下冷场Z参数进行线性插值运算,可消除沟道分布电阻和栅极泄漏电流对寄生电阻的影响;再利用热场S参数对寄生参数部分进行去嵌,可提取得到本征参数。分析表明,此模型和算法提高了模型拟合精度,S参数的仿真结果与测试数据在200MHz到40GHz的频率范围内均符合很好,误差不到2%。     

Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field‐Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk

This paper presents a stochastic logic‐based method for quantitative risk assessment using fault tree analysis (FTA) that can take into account both types of uncertainties including objective and subjective uncertainties. In the proposed method, each fault tree gate is translated to its corresponding stochastic logic template and then is implemented on a field programmable gate array (FPGA). Because the analysis does not utilize any transformation methods, the results of analysis are more accurate than those methods which are based on transformation from possibility to probability distributions or vice versa. Experimental results for a benchmark fault tree show that this method accelerates analysis time compared to conventional hybrid uncertainty analysis method and transformation methods. The efficiency of the proposed method is demonstrated by implementation in a real steel structure project. The quantitative risk assessment is performed for the incomplete penetration as one of the defects encountered in arc welding process, and its results are compared with transformation methods. The comparison results show the proposed hybrid uncertainty analysis method is also more accurate in comparison to the transformation‐based approaches. Copyright © 2016 John Wiley & Sons, Ltd.     

Threshold Voltage Control of Multilayered MoS2 Field‐Effect Transistors via Octadecyltrichlorosilane and their Applications to Active Matrixed Quantum Dot Displays Driven by Enhancement‐Mode Logic Gates

In recent past, for next‐generation device opportunities such as sub‐10 nm channel field‐effect transistors (FETs), tunneling FETs, and high‐end display backplanes, tremendous research on multilayered molybdenum disulfide (MoS₂) among transition metal dichalcogenides has been actively performed. However, nonavailability on a matured threshold voltage control scheme, like a substitutional doping in Si technology, has been plagued for the prosperity of 2D materials in electronics. Herein, an adjustment scheme for threshold voltage of MoS₂ FETs by using self‐assembled monolayer treatment via octadecyltrichlorosilane is proposed and demonstrated to show MoS₂ FETs in an enhancement mode with preservation of electrical parameters such as field‐effect mobility, subthreshold swing, and current on–off ratio. Furthermore, the mechanisms for threshold voltage adjustment are systematically studied by using atomic force microscopy, Raman, temperature‐dependent electrical characterization, etc. For validation of effects of threshold voltage engineering on MoS₂ FETs, full swing inverters, comprising enhancement mode drivers and depletion mode loads are perfectly demonstrated with a maximum gain of 18.2 and a noise margin of ≈45% of 1/2 V_DD. More impressively, quantum dot light‐emitting diodes, driven by enhancement mode MoS₂ FETs, stably demonstrate 120 cd m^?2 at the gate‐to‐source voltage of 5 V, exhibiting promising opportunities for future display application.     

Controllable P‐ and N‐Type Conversion of MoTe2 via Oxide Interfacial Layer for Logic Circuits

To realize basic electronic units such as complementary metal‐oxide‐semiconductor (CMOS) inverters and other logic circuits, the selective and controllable fabrication of p‐ and n‐type transistors with a low Schottky barrier height is highly desirable. Herein, an efficient and nondestructive technique of electron‐charge transfer doping by depositing a thin Al₂O₃ layer on chemical vapor deposition (CVD)‐grown 2H‐MoTe₂ is utilized to tune the doping from p‐ to n‐type. Moreover, a type‐controllable MoTe₂ transistor with a low Schottky barrier height is prepared. The selectively converted n‐type MoTe₂ transistor from the p‐channel exhibits a maximum on‐state current of 10 µA, with a higher electron mobility of 8.9 cm² V^?1 s^?1 at a drain voltage (V_ds) of 1 V with a low Schottky barrier height of 28.4 meV. To validate the aforementioned approach, a prototype homogeneous CMOS inverter is fabricated on a CVD‐grown 2H‐MoTe₂ single crystal. The proposed inverter exhibits a high DC voltage gain of 9.2 with good dynamic behavior up to a modulation frequency of 1 kHz. The proposed approach may have potential for realizing future 2D transition metal dichalcogenide‐based efficient and ultrafast electronic units with high‐density circuit components under a low‐dimensional regime.