Hydrodynamic hot-electron transport simulation based on the Monte Carlo method

A hydrodynamic hot electron model is used to study electron transport through a submicron N⁺ --- N --- N⁺ GaAs structure. This study is used to investigate improvements which the unique features of this model offer to analysis of devices operating under nonstationary transport conditions. The model is based upon semiclassical “hydrodynamic” conservation equations for the average carrier density, momentum and energy. The general model includes particle relaxation times, momentum relaxation times, energy relaxation times, electron temperature tensors and heat flow vectors as a function of average carrier energy for the Γ, X and L valleys of GaAs. For this study, we utilized a simplified single electron gas version of our model to clearly reveal the impact of the nonstationary terms in the model. Results from both a drift-diffusion model approach and a Monte Carlo analysis are used to show the relative accuracy and facility this new model offers for investigating practical submicron device structures operating under realistic conditions.     

Excellent immunity of GIDL to hot-electron stress in reoxidizednitrided gate oxide MOSFET's

The authors present an investigation of the enhancement in gate-induced drain leakage (GIDL) caused by hot-electron stress in MOSFETs with control oxides, nitrided oxides, and reoxidized nitrided oxides as gate dielectrics. The contributions of interface state generation and electron trapping to GIDL enhancement in these MOSFETs were compared based on stress condition and stress time dependencies. Although no improvement resulted at large drain biases, under low drain voltage conditions, reoxidized nitrided oxides exhibited less GIDL enhancement under hot-electron stress than a nitrided oxide that was not reoxidized     

Latch and hot-electron gate current in accumulation-mode SOIp-MOSFET's

Simultaneous measurements of drain and gate currents in short-channel accumulation-mode SOI p-MOSFET'MOs demonstrate that a latch mechanism may occur in these devices and induce an anomalous behavior of the hot-electron gate current: distortion of I_g(V _g) curves, hysteresis and excessively high gate current values. 2-D MEDICI simulations based on the lucky-electron model qualitatively reproduce the measurements in the latch regime, and explain the unusual gate current dependence on drain and gate biases. The results are of relevance for reliability and modeling issues     

1.5 nm direct-tunneling gate oxide Si MOSFET's

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 μm, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA/μm and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 μm at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used     

Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.     

Component placement in VLSI circuits using a constant pressure Monte Carlo method

When laying out a VLSI circuit on a silicon wafer the object is to pack the components of the circuit onto a wafer of minimum area subject to a variety of conflicting constraints associated with electrical interconnections among the components and input/ output connections. A constant pressure Monte Carlo method is applied to an idealized component placement problem where the object is to pack different rectangular components onto a square of minimum area with a subsidiary objective of minimizing the total length of wires interconnecting the components. The Monte Carlo method is found to be remarkably effective in solving this idealized problem. No other method for solving this problem is known.     

Monte Carlo Modeling of a Light-Pipe Radiation Thermometer

Light-pipe radiation thermometers (LPRTs) are widely used to monitor temperature during thermal processing of materials, particularly semiconductor wafer rapid thermal processing. According to the International Technology Roadmap for Semiconductors 2004, temperatures for semiconductor wafer processing should be measurable to within an uncertainty of plusmn1.5 degC at 1000 degC with temperature calibration traceable to International Temperature Standard-90. To achieve this accuracy level, the radiation signal transport process inside the light-pipe probe has to be fully understood. Few studies have been conducted to model the radiation transfer of LPRTs. In this paper, a Monte Carlo model has been created to simulate the signal transport from the measurement surface through the light-pipe probe. The model predicts the acceptance angle or aperture of the light-pipe. We also investigated the effect of nonspecular reflections caused by the sidewall surface roughness of the light-pipe probe using this model     

Successive charging/discharging of gate oxides in SOI MOSFET's bysequential hot-electron stressing of front/back channel

Hot-hole injection into the opposite channel of silicon-on-insulator (SOI) MOSFETs under hot-electron stress is reported. Sequential front/back-channel hot-electron stressing results in successive hot-electron/-hole injection, causing the threshold voltage to increase and decrease accordingly. This ability to inject hot holes into the opposite gate oxide can be used as an additional tool for studying the degradation mechanisms. Furthermore, it can be explored for possible use in designing SOI flash memory cells with back-channel-based erasing schemes     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Reduced hot-electron effects in MOSFET's with an optimized LDD Structure

A comparison of device degradation due to hot-electron injection is made for conventional MOSFET's and lightly doped drain (LDD) structures. The studies indicate that, for an optimized LDD structure, critical device parameters, such as threshold voltage, transconductance, and linear and saturated current drives, show significantly reduced degradation when subjected to accelerated life testing. These results imply long-term stability for LDD devices used in VLSI circuits.     

Monte Carlo analysis of a low power domino gate under parameter fluctuation

Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique (DTV) in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.     

参数浮动下低功耗多米诺门的蒙特卡罗分析

Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique （DTV） in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.     

Modeling for an AlGaAs/GaAs heterostructure device using Monte Carlo simulation

Two-dimensional electron gas behavior in an AlGaAs/GaAs heterostructure FET has been analyzed using the Monte Carlo method. In the channel region, it is assumed that the electrons are subjected to a two-dimensional scattering process. In the other regions, three-dimensional scattering rates are assumed. It is predicted that, in an actual device with 1.20-µm gate length, the transconductance of 250 and 450 mS/mm can be attained at 300 and 77 K, respectively. More efficient performance is possible with improvements in the device structure.     

Monte Carlo simulation of electron transport efficiency of an InGaAs/InP hot-electron transistor

Electron transport efficiency of an InGaAs/InP hot-electron transistor (HET) is determined by a Monte Carlo method including alloy scattering in an InGaAs base. Results are compared with those of a GaAs/AlGaAs HET. It is found that the InGaAs/InP HET offers a higher current gain than that of a GaAs/AlGaAs HET by an order of magnitude.     

A simple method to characterize substrate current in MOSFET's

Experimental verification of substrate current characteristics is thoroughly carried out. VDS- VDSAT, instead of VDS, is shown to be the driving force of all hot-electron effects. A simple relationship between substrate current and VDS- VDSATis found. This relationship provides a convenient tool to characterize the substrate current or the channel electric field, and, hence, all hot-electron effects. Measurements of ISUB/IDand VDS- VDSATat two bias points and any one channel length are sufficient to fully characterize the substrate currents for all channel lengths VDS's and VG's for a given technology.     

Monte Carlo Simulations of Thermal Conductivity in Nanoporous Si Membranes

We present a Monte Carlo study of heat transport in Si nanomeshes. Phonons are treated semiclassically as particles of specific energy and velocity that undergo phonon–phonon scattering and boundary scattering on the surfaces of the nanomesh pores. We investigate the influence of: (1) geometric parameters such as the pore arrangement/randomness and porosity, and (2) the roughness amplitude of the pore surfaces on the thermal conductivity of the nanomeshes. We show that the nanomesh porosity has a strong detrimental influence on the thermal conductivity. Boundary roughness still degrades the thermal conductivity, but its influence is smaller.     

Fabrication of inversion-type n-channel MOSFET's using cubic-SiC on Si

Inversion-type n-channel MOSFET's of cubic-SiC were successfully fabricated. Cubic-SiC was grown on Si     

A new approach to simulating n-MOSFET gate current degradation byincluding hot-electron induced oxide damage

A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N_it ) and oxide trapped charge (Q_ox) were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N_it and Q_ox has thus been proposed. Furthermore, the individual contributions of N_it and Q_ox to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I_G,max. Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and flash EEPROM devices     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

Analysis of flash lamp structure using Monte Carlo photon tracing method

By analyzing the flash lamp structure, better illumination distributions in the lamp's field of view can be obtained. Instead of geometrical optical approaches, the Monte Carlo photon tracing method was used here to trace the photon tracks in a three-dimensional space. The models of elemental structures in a camera flash lamp, such as the flash tube, reflector and focus lens, were set up by introducing the cosinusoidal random number and other mathematical methods. Initially, the single photon was traced in the flash lamp by using the Monte Carlo method to simulate various photon tracks. A large sum of photons was then generated to simulate the real situation in the flash lamp. Finally, a group of structural parameters was applied to verify the simulative computer program. The output light intensity distributions at different angles of view in the orthogonal directions meet the ISO standards and are very close to the measured ones. Hence, the Monte Carlo photon tracing method in the design of flash lamps has been proven to be applicable and useful.