Parallel modified signed-digit arithmetic using an optoelectronic shared content-addressable-memory processor

Addition is the most primitive arithmetic operation in digital computation. Other arithmetic operations such as subtraction, multiplication, and division can all be performed by addition together with some logic operations. With the binary number system, addition speed is inevitably limited by the carry-propagation schemes. On the other hand, carry-free addition is possible when the modified signed-digit (MSD) number representation is used. We propose a novel optoelectronic scheme to handle the parallel MSD addition and subtraction operations. An optoelectronic shared content-addressable memroy is introduced. The shared content-addressable memory uses free-space optical processing to handle the large amount of parallel memory access operations and uses electronics to postprocess and derive logic decisions. We analyze the accuracy that the required optical hardware can deliver by using a statistical cross-talk-rate model that we propose. We also evaluate other important device and system performanceparameters, such as the memory capacity or the maximum number of parallel bits the adder can handle in terms of a given cross-talk rate at a certain repetition rate, the corresponding diffraction-limited memory density, and the system's power efficiency. To confirm the underlining operational principles of the proposed optoelectronic shared content-addressable-memory MSD adder, we design and perform initial experiments for handling 8-bit MSD number addition and subtraction and present the results.     

Microring resonator-based logic module for all optical information processing

We propose an all-optical logic module based on switching in microring resonators due to free carrier induced two-photon absorption. The proposed logic module is implemented using two microring resonators, and with the addition of beam combiner(s), it can be configured to perform different arithmetic and logical operations based on different combinations of input bits. The design is analysed mathematically in terms of coupling between the ring resonator and waveguides. The logic module can also be configured as a half adder and a half subtractor, suitable for all-optical information processing applications. Simulation results are in good agreement with the theoretical calculations and are presented in this paper.     

All-optical quaternary logic gates

Conventional binary logic based operations restrict the speed of operations as well as information handling capacity. A way to overcome these limitations is the implementation of multivalued logic operations in the optical domain. Multivalued logic operations not only enhance the data handling capacities but also increase the speed of processing. integrating enormous potential bandwidth of optical fiber as information carrying medium and faster optoelectronic/optical switches with no hardware complexity. A new method is proposed for the implementation of all-optical quaternary inversion, MAX, MIN, and equality operations using frequency-encoded data. Cross phase modulation-based frequency conversion, polarization switch (PSW) characteristics of a semiconductor optical amplifier (SOA), frequency routing by a wave division multiplexer (MUX), and a demultiplexer (DMUX) have been exploited to implement the desired quaternary logic operations. Simulation results support the feasibility of the proposed scheme.     

Direct-coupled high speed adder by using Josephson junction

This paper presents the latest design work of high speed adder logic based on Josephson elements. The Josephson adder uses a novel exclusive-OR logic and performs high speed carry propagation technique. The idea of directionality is also undertaken to avoid the necessary distortion in carry signal. The principle of operation with salient feature of simulation of the adder are presented in full detail. Necessary checks for carry skip and other fabrication parameters are investigated using detailed model of the device based on its highly miniaturized size. The results of the simulation show that the nominal delay of the adder logic is 20 ps/stage and average power dissipation is 47 μW/stage. Authors have mainly stressed upon how to obtain ultra fast speed at the cost of very low power dissipation of the presented adder with its small size.     

A novel integer programming formulation with logic cuts for the U-shaped assembly line balancing problem

U-shaped assembly lines are regarded as an efficient configuration in Just-In-Time manufacturing. Balancing the workload in these lines is an unsolved problem that attracted significant research within the past two decades. We present a novel integer programming formulation for U-shaped line balancing problems, where cycle time, the interval between two consecutive outputs, is known and the aim is to minimize the number of workstations. To enhance the efficiency of the LP relaxation of the new formulation, we present three types of logic cuts (assignable-station-cuts, task-assignment-cuts and knapsack-cuts) that exploit the inherent logic of the problem structure. The new formulation and logic cuts are tested on an extensive set of benchmark problems to provide a comparative analysis with the existing models in the literature. The results show that our novel formulation augmented by assignable-station-cuts is significantly better than the previous formulations.     

A scheme of developing frequency encoded tristate-optical logic operations using semiconductor optical amplifier

The ever increasing demand for very fast and agile optical networks requires very fast execution of different optical and logical operations as well as large information handling capacities at the same time. In conventional binary logic based operations the information is represented by two distinct states only (0 and 1 state). It limits the large information handling capacity and speed of different arithmetic and optical logic operations. Tristate based logic operations can be accommodated with optics successfully in data processing, as this type of operation can enhance the speed of operation as well as increase the information handling capacity. Here in this communication the author proposes a new method to implement all-optical different logic gates with tristate logic using the frequency-encoding principle. The frequency encoding/decoding based optical communication has distinctly great advantages because the frequency is the fundamental character of an optical signal and it preserves its identity throughout the communication. The principle of the rotation of the state of polarization of a probe beam through semiconductor optical amplifier (SOA), frequency routing property of an optical add/drop multiplexer (AD) and high frequency conversion property of reflecting semiconductor optical amplifiers (RSOA) have been exploited here to implement the desired AND, OR, NAND and NOR logic operations with tristate logic.     

Intelligent Cloud Based Load Balancing System Empowered with Fuzzy Logic

Cloud computing is seeking attention as a new computing paradigm to handle operations more efficiently and cost-effectively. Cloud computing uses dynamic resource provisioning and de-provisioning in a virtualized environment. The load on the cloud data centers is growing day by day due to the rapid growth in cloud computing demand. Elasticity in cloud computing is one of the fundamental properties, and elastic load balancing automatically distributes incoming load to multiple virtual machines. This work is aimed to introduce efficient resource provisioning and de-provisioning for better load balancing. In this article, a model is proposed in which the fuzzy logic approach is used for load balancing to avoid underload and overload of resources. A Simulator in Matlab is used to test the effectiveness and correctness of the proposed model. The simulation results have shown that our proposed intelligent cloud-based load balancing system empowered with fuzzy logic is better than previously published approaches.     

Simple and universal platform for logic gate operations based on molecular beacon probes

A new platform technology is herein described with which to construct molecular logic gates by employing the hairpin-structured molecular beacon probe as a basic work unit. In this logic gate operation system, single-stranded DNA is used as the input to induce a conformational change in a molecular beacon probe through a sequence-specific interaction. The fluorescent signal resulting from the opening of the molecular beacon probe is then used as the output readout. Importantly, because the logic gates are based on DNA, thus permitting input/output homogeneity to be preserved, their wiring into multi-level circuits can be achieved by combining separately operated logic gates or by designing the DNA output of one gate as the input to the other. With this novel strategy, a complete set of two-input logic gates is successfully constructed at the molecular level, including OR, AND, XOR, INHIBIT, NOR, NAND, XNOR, and IMPLICATION. The logic gates developed herein can be reversibly operated to perform the set-reset function by applying an additional input or a removal strand. Together, these results introduce a new platform technology for logic gate operation that enables the higher-order circuits required for complex communication between various computational elements.     

Digital clocks: simple Boolean models can quantitatively describe circadian systems

The gene networks that comprise the circadian clock modulate biological function across a range of scales, from gene expression to performance and adaptive behaviour. The clock functions by generating endogenous rhythms that can be entrained to the external 24-h day–night cycle, enabling organisms to optimally time biochemical processes relative to dawn and dusk. In recent years, computational models based on differential equations have become useful tools for dissecting and quantifying the complex regulatory relationships underlying the clock''s oscillatory dynamics. However, optimizing the large parameter sets characteristic of these models places intense demands on both computational and experimental resources, limiting the scope of in silico studies. Here, we develop an approach based on Boolean logic that dramatically reduces the parametrization, making the state and parameter spaces finite and tractable. We introduce efficient methods for fitting Boolean models to molecular data, successfully demonstrating their application to synthetic time courses generated by a number of established clock models, as well as experimental expression levels measured using luciferase imaging. Our results indicate that despite their relative simplicity, logic models can (i) simulate circadian oscillations with the correct, experimentally observed phase relationships among genes and (ii) flexibly entrain to light stimuli, reproducing the complex responses to variations in daylength generated by more detailed differential equation formulations. Our work also demonstrates that logic models have sufficient predictive power to identify optimal regulatory structures from experimental data. By presenting the first Boolean models of circadian circuits together with general techniques for their optimization, we hope to establish a new framework for the systematic modelling of more complex clocks, as well as other circuits with different qualitative dynamics. In particular, we anticipate that the ability of logic models to provide a computationally efficient representation of system behaviour could greatly facilitate the reverse-engineering of large-scale biochemical networks.     

Efficient Energy Optimized Faithful Adder with Parallel Carry Generation

Approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant applications. This work proposes an approximate adder that to optimize area delay and achieve energy efficiency using Parallel Carry (PC) generation logic. For ‘n’ bits in input, the proposed algorithm use approximate addition for least n/2 significant bits and exact addition for most n/2 significant bits. A simple OR logic with no carry propagation is used to implement the approximate part. In the exact part, addition is performed using 4-bit adder blocks that implement PC at block level to reduce node capacitance in the critical path. Evaluations reveal that the maximum error of the proposed adder confines not more than 2^n/2. As an enhancement of the proposed algorithm, we use the Error Recovery (ER) module to reduce the average error. Synthesis results of Proposed-PC (P-PC) and Proposed-PCER (P-PCER) adders with n-16 in 180nm Application Specific Integrated Circuit (ASIC) PDK technology revealed 44.2% & 41.7% PDP reductions and 43.4% & 40.7% ADP reductions, respectively compared to the latest best approximate design compared. The functional and driving effectiveness of proposed adders are examined through digital image processing applications.     

A Parallel Simulated Annealing Architecture for Model Updating in Wireless Sensor Networks

In recent years, wireless sensing technologies have provided a much sought-after alternative to expensive cabled monitoring systems. Wireless sensing networks forego the high data transfer rates associated with cabled sensors in exchange for low-cost and low-power communication between a large number of sensing devices, each of which features embedded data processing capabilities. As such, a new paradigm in large-scale data processing has emerged; one where communication bandwidth is somewhat limited but distributed data processing centers are abundant. By taking advantage of this grid of computational resources, data processing tasks once performed independently by a central processing unit can now be parallelized, automated, and carried out within a wireless sensor network. By utilizing the intelligent organization and self-healing properties of many wireless networks, an extremely scalable multiprocessor computational framework can be developed to perform advanced engineering analyses. In this study, a novel parallelization of the simulated annealing stochastic search algorithm is presented and used to update structural models by comparing model predictions to experimental results. The resulting distributed model updating algorithm is validated within a network of wireless sensors by identifying the mass, stiffness, and damping properties of a three-story steel structure subjected to seismic base motion.     

A workload balancing genetic algorithm for the quay crane scheduling problem

This paper proposes a novel genetic algorithm to deal with the quay crane scheduling problem (QCSP), which is known to be one of the most critical tasks in terminal operations because its efficiency and the quality of the schedule directly influence the productivity of the terminal. QCSP has been studied intensively in recent years. Algorithms in this field are concerned in the solution quality obtained and the required computational time. As QCSP is known to be NP-hard, heuristic approaches are widely adopted. The genetic algorithm proposed is constructed with a novel workload balancing heuristics, which is capable of considering the loading conditions of different quay cranes (QCs) during the reassignment of task-to-QC. The idea is modelled as a fuzzy logic controller to guide the mutation rate and mutation mechanism of the genetic algorithm. As a result, the proposed algorithm does not require any predefined mutation rate. Meanwhile, the genetic algorithm can more adequately reassign tasks to QCs according to the QCs’ loading condition throughout the evolution. The proposed algorithm has been tested with the well-known benchmark problem sets in this field and produces some new best solutions in a much shorter computational time.     

Extended coding for optical array logic

We present extended coding for optical array logic (OAL) to avoid the marginal effect. The marginal effect is defined as an effect caused by the finite size of the image region, and it is a problem in massively parallel processing by OAL. OAL is a paradigm of optical computing suitable for optical implementation utilizing image coding and discrete correlation. To avoid the marginal effect in the context of OAL, we propose a new coding rule and consider possible operations with this coding. With extended coding, binary data can be identified from background with the same number of pixels as that used in the original OAL. Simulation results of the operations verify the correctness of the proposed technique.     

Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics

Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems.Here,we show that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-based memristor array.Although memristive logic-in-memory circuits have been previously reported,the requirements of additional components and the large variation of memristors have limited demonstrations to simple gates within a few operation cycles on rigid substrates only.Using memristor-aided logic (MAGIC) architecture requiring only memristors and pV3D3-memristor with good uniformity on a flexible substrate,for the first time,we experimentally demonstrated our implementation of MAGIC-NOT and-NOR gates during multiple cycles and even under bent conditions.Other functions,such as OR,AND,NAND,and a half adder,are also realized by combinations of NOT and NOR gates within a crossbar array.This research advances the development of novel computing architecture with zero static power consumption for batterypowered flexible electronic systems.     

Logic Computing with Stateful Neural Networks of Resistive Switches

Brain‐inspired neural networks can process information with high efficiency, thus providing a powerful tool for pattern recognition and other artificial intelligent tasks. By adopting binary inputs/outputs, neural networks can be used to perform Boolean logic operations, thus potentially surpassing complementary metal–oxide–semiconductor logic in terms of area efficiency, execution time, and computing parallelism. Here, the concept of stateful neural networks consisting of resistive switches, which can perform all logic functions with the same network topology, is introduced. The neural network relies on physical computing according to Ohm's law, Kirchhoff 's law, and the ionic migration within an output switch serving as the highly nonlinear activation function. The input and output are nonvolatile resistance states of the devices, thus enabling stateful and cascadable logic operations. Applied voltages provide the synaptic weights, which enable the convenient reconfiguration of the same circuit to serve various logic functions. The neural network can solve all two‐input logic operations with just one step, except for the exclusive‐OR (XOR) needing two sequential steps. 1‐bit full adder operation is shown to take place with just two steps and five resistive switches, thus highlighting the high efficiencies of space, time, and energy of logic computing with the stateful neural network.     

新型8管一位全加器电路设计

通过对已有全加器电路的研究与分析,提出了仅需8个晶体管的新型全加器单元.新电路包括2个3管同或门模块和1个选择器模块.在台积电(TSMC)0.18μm互补氧化物半导体(CMOS)工艺器件参数下经电路模拟程序(HSPICE)进行性能测试,与现有典型的全加器相比,新电路在晶体管数目、功耗和功耗延迟积有较大的优势.     

Multispectral plasmon induced transparency in coupled meta-atoms

We introduce an approach enabling construction of a scalable metamaterial media supporting multispectral plasmon induced transparency. The composite multilayered media consist of coupled meta-atoms with radiant and subradiant hybridized plasmonic modes interacting through the structural asymmetry. A perturbative model incorporating hybridization and mode coupling is introduced to explain the observed novel spectral features. The proposed scheme is demonstrated experimentally by developing a lift-off-free fabrication scheme that can automatically register multiple metamaterial layers in the transverse plane. This metamaterial which can simultaneously enhance nonlinear processes at multiple frequency domains could open up new possibilities in optical information processing.     

Integrated all-optical logic and arithmetic operations with the help of a TOAD-based interferometer device--alternative approach

Interferometric devices have drawn a great interest in all-optical signal processing for their high-speed photonic activity. The nonlinear optical loop mirror provides a major support to optical switching based all-optical logic and algebraic operations. The gate based on the terahertz optical asymmetric demultiplexer (TOAD) has added new momentum in this field. Optical tree architecture (OTA) plays a significant role in the optical interconnecting network. We have tried to exploit the advantages of both OTA- and TOAD-based switches. We have proposed a TOAD-based tree architecture, a new and alternative scheme, for integrated all-optical logic and arithmetic operations.     

Building a Trust Model for Secure Data Sharing (TM-SDS) in Edge Computing Using HMAC Techniques

With the rapid growth of Internet of Things (IoT) based models, and the lack amount of data makes cloud computing resources insufficient. Hence, edge computing-based techniques are becoming more popular in present research domains that makes data storage, and processing effective at the network edges. There are several advanced features like parallel processing and data perception are available in edge computing. Still, there are some challenges in providing privacy and data security over networks. To solve the security issues in Edge Computing, Hash-based Message Authentication Code (HMAC) algorithm is used to provide solutions for preserving data from various attacks that happens with the distributed network nature. This paper proposed a Trust Model for Secure Data Sharing (TM-SDS) with HMAC algorithm. Here, data security is ensured with local and global trust levels with the centralized processing of cloud and by conserving resources effectively. Further, the proposed model achieved 84.25% of packet delivery ratio which is better compared to existing models in the resulting phase. The data packets are securely transmitted between entities in the proposed model and results showed that proposed TM-SDS model outperforms the existing models in an efficient manner.     

Alternate State Variables for Emerging Nanoelectronic Devices

We provide an outlook of some important state variables for emerging nanoelectronic devices. State variables are physical representations of information used to perform information processing via memory and logic functionality. Advances in material science, emerging nanodevices, nanostructures, and architectures have provided hope that alternative state variables based on new mechanisms, nanomaterials, and nanodevices may indeed be plausible. We review and analyze the computational advantages that alternate state variables may possibly attain with respect to maximizing computational performance via minimum energy dissipation, maximum operating switching speed, and maximum device density.