Analog statistical simulation for bipolar integrated circuits

Analog circuit design automation continues to gain attention in methods to improve, automate, and reduce design cycle time. These techniques address the needs of improving design for functionality, however the importance of design for manufacturability continues to be neglected. The emphasis of design for manufacturability is shown when the quality of a part is measured. Parts designed with no consideration for process/design variations result in poor yield. To address the need in analog design for manufacturability, new techniques that involve the areas of physical process, geometric modeling of electrical parameters, and statistical simulation techniques using independent process parameters, yield and Cpk analysis are defined and implemented. Results from these techniques provide the analog designer with the ability to simulate and predict circuit quality with process and design variations. To support the defined techniques, a design tool called MSTAT (Motorola Statistical Analysis Tool) is developed. Results of these techniques accompanied with MSTAT output is presented.     

Silicon bipolar integrated circuits for multigigabit-per-secondlightwave communications

Recent results on silicon bipolar ICs for lightwave communications in the multigigabits-per second (Gb/s) range are presented. These state-of-the-art results demonstrate the inherent speed difference between the different types of basic circuits. With the fastest ones (multiplexing and demultiplexing), bit rates above 10 Gb/s are achieved, even with production technologies. The technologies, as well as circuit and design principles to achieve such high operating speeds, are discussed, and some experimental examples are described in more detail. Moreover, the high-speed potential of present 1-μm silicon bipolar technologies is demonstrated by the simulation of carefully optimized communication ICs. With most of the basic circuits, bit rates above 10 Gb/s, and in some cases above 20 Gb/s, are achievable     

Arsenic-doped polycrystalline silicon film for bipolar integrated circuits

The advantages of the use of As-doped polycrystalline silicon film over that of As-doped glass film in the fabrication of high speed bipolar integrated circuits have been shown. The films have been used for doping buried layer and emitter. Deposition conditions optimized for the As-doped polycrystalline silicon film allows low junction leakage to be attained with low pipe density. During the course of the work the mechanism for the formation of pipes have been suggested.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

Heterostructure bipolar transistors and integrated circuits

Two new epitaxial technologies have emerged in recent years (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)), which offer the promise of making highly advanced heterostructures routinely available. While many kinds of devices will benefit, the principal and first beneficiary will be bipolar transistors. The underlying central principle is the use of energy gap variations beside electric fields to control the forces acting on electrons and holes, separately and independently of each other. The resulting greater design freedom permits a re-optimization of doping levels and geometries, leading to higher speed devices. Microwave transistors with maximum oscillation frequencies above 100 GHz and digital switching transistors with switching times below 10 ps should become available. An inverted transistor strucure with a smaller collectors on top and a larger emitter on the bottom becomes possible, with speed advantages over the common "emitter-up" design. Double-heterostructure (DH) transistors with both wide-gap emitters and collectors offer additional advantages. They exhibit better performance under saturated operation. Their emitters and collectors may be interchanged by simply changing biasing conditions, greatly simplifying the architecture of bipolar IC's. Examples of heterostructure implementations of I²L and ECL are discussed. The present overwhelming dominance of the compound semiconductor device field by FET's is likely to come to an end, with bipolar devices assuming an at least equal role, and very likely a leading one.     

Devices and circuits for bipolar (V)LSI

It is shown that bipolar circuits can continue to play an important role in high-performance LSI and VLSI circuits, because power supply voltages and logic swings can be minimized independently of dimensions, and because the speed degradation due to on-chip wiring capacitances is less severe than in MOSFET/MESFET types of circuit. General performance improvements (in speed and packing density) of logic gates are obtained by increasing transistor fT, and decreasing parasitic capacitances, series resistances and device areas, by using oxide isolation, self-aligned techniques and polysilicon electrodes. Fast switching diodes (such as Schottky barrier diodes and lateral polydiodes) improve the flexibility of circuit design. Logic circuits (such as I²L, LS, DTL, ISL, STL, ECL, and NTL), which already perform in LSI and VLSI circuits or are realistic proposals for them, are discussed.     

Silicon bipolar integrated circuits for multi-Gb/second opticalcommunication systems

The authors discuss several important circuits for fiber-optic transmission, implemented in an advanced silicon bipolar integrated circuit technology. Specifically, the authors discuss the design considerations and measured performance of a 2:1 multiplexer, front end receiver, limiting amplifier, and decision circuit IC. Also discussed are three hybrid circuit modules: a 2:1 multiplexer, 1:2 demultiplexer, and parallel processing decision circuit. These ICs and hybrid circuit modules operate at multi-Gb/s data rates. The performance of these ICs indicates that advanced silicon bipolar integrated circuits with their high speed, functionality and low cost potential could play an important role in alleviating the electronic bottleneck in future multigigabit optical communication systems     

Thermal design and simulation of bipolar integrated circuits

Keeping device operating temperatures within reasonable limits is necessary for reliability of all ICs and important for achieving the expected performance for many ICs. GaAs heterojunction bipolar transistors (HBTs) offer high speed and good device matching characteristics that are attractive for many high-speed circuits, but they are more susceptible than other IC technologies to the unexpected generation of very high junction temperatures. The reasons for this tendency are discussed, and an HBT sample-and-hold (S/H) circuit that had device temperature rises of over 300°C is described. To address this problem, a new thermal simulation tool called ThCalc was created. ThCalc calculates the temperature profile of an IC and runs fast enough to allow calculations on a whole chip. ThCalc was used to redesign the S/H IC to reduce the largest temperature rise by a factor of 2.7 with a minimal impact on circuit size     

Determination of the stress level for voltage screen of integrated circuits

Voltage screen is a method to screen out products that suffer from defectivity related issues. A risk associated with voltage screen is that the applied voltage is too severe and damages the product. Most papers dealing with voltage screen determine the stress voltage by a general rule of thumb (focusing on one specific mechanism) without taking into account the particularities and the knowledge of the specific process.This paper describes a general approach to determine a safe level for voltage screening of products. In this approach, the onset of the wearout phase is not allowed to shift more than 1%. All the information needed to determine the voltage value is in general typically available from the process reliability tests performed as part of the process qualification.     

A GaAs/AlGaAs double-heterojunction device functioning as a bipolar transistor and injection laser for optoelectronic integrated circuits

A GaAs/AlGaAs double-heterojunction bipolar transistor (DHBT) is developed which also functions as a transverse-injection laser. The epitaxial layers for the DHBT's are grown by metalorganic vapor phase epitaxy (MOVPE). Experimentation reveals a transistor current gain of ∼ 10 and a pulsed lasing threshold of 230 mA at room temperature.     

Design of RF integrated circuits using SiGe bipolar technology

We report on design aspects and the implementation of radio-frequency integrated circuits using TEMIC's SiGe technology. The differences between the device parameters of silicon bipolar junction transistor and silicon germanium heterojunction bipolar transistor technology and their influence on IC design are discussed. Design and measurement results of RFICs, including low noise amplifier, power amplifier, and single-pole, double-throw antenna switch for application in a 1.9 GHz digital enhanced cordless telecommunications RF front end are presented     

Efficient analysis of microstrip-coupled nonradiative dielectric(NRD) resonators for hybrid integrated circuits

Nonradiative dielectric (NRD) resonators have been recently known as excellent stabilizing components for the design of a new class of oscillators based on hybrid integration of planar circuits and NRD-guides. However, an accurate characterization of such a component is needed in order to develop efficient computer-aided-design programs. In this paper, a hybrid planar integrated circuit comprising an NRD resonator is accurately modeled and is coupled to input and output planar microstrip circuits by means of long slots located on the top ground plane of the NRD structure. A reciprocity approach is used to solve the coupling problem between the resonator and microstrip lines. A modal expansion of the field equations has been applied to the NRD resonator in obtaining its rigorous field expressions. Finally, a transmission-line analysis is proposed for the structure, and scattering parameters have been calculated for different slot positions. Results are discussed for various parametric effects on coupling and Q-factor characteristics     

Characterisation of electromagnetic susceptibility of integrated circuits using near-field scan

A susceptibility characterisation test for integrated circuits using a miniature magnetic near-field probe is described. The method is efficient up to a frequency of 6 GHz and maps immunity to radiated fields     

A 1-μm polysilicon self-aligning bipolar process for low-powerhigh-speed integrated circuits

A double-poly-Si self-aligning bipolar process employing 1-μm lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f_T =14 GHz at V_BC=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0×2.0 μm² a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz     

ANDREI-a minicomputer nonlinear analysis program for integrated circuits

A circuit analysis program, ANDREI, has been developed which can be run on a 32K 16-bit word minicomputer with a disk unit. A novel virtual storage scheme is used to save internal memory required by large arrays. The nonlinear DC and transient and small-signal AC analyses of circuits up to 150 nodes and 150 elements can be performed in the present version. Semiconductor device models for diodes, bipolar junction transistors, junction- and MOSFETs are built in. ANDREI runs presently on a 32K VARIAN 73 minicomputer.     

The implanted zener diode (IZD) as an input protection device for MOS integrated circuits

Phosphorus implantation, performed prior to the major standard process steps in p-channel technology, is used for a well controllable reduction of the breakdown voltage of planar diodes down to values which makes them suited as protection devices. In these devices the walk-out of the breakdown voltage, which is characteristic for the field-plated types of protective devices is almost completely eliminated. The dynamic resistance of the implanted diodes can be considerably reduced by providing a second p⁺diffusion which gives rise to parasitic bipolar transistor operation during breakdown. The dynamic resistance is found to be linearly dependent on the width of the space charge layer which is ascribed to microplasma phenomena occuring during breakdown. The overvoltages against which the new devices can offer protection when used in a distributed resistance configuration of 200-µm width, are shown to be in the 10-60-kV range.     

Recent progress in optoelectric integrated circuits (OEIC's)

Recent developments in both GaAs- and InP-based opto-electronic circuits (OEIC's) which incorporate both optoelectronic and electronic devices on the same semiconductor substrates will be discussed. Several key technologies required for optoelectronic integration and the present status of the technology are explained by reviewing some of OEIC transmitters and receivers that have been realized up to now. Possibilities of application of OEIC's and further technological challenges to enhance the advantages of OEIC's are discussed.     

A generalized surface-volume integral-equation (SVIE) approach for analysis of hybrid planar/NRD-guide integrated circuits

A generalized surface-volume integral-equation approach (SVIE) has been proposed and developed for accurate modeling and analysis of hybrid planar/nonradiating dielectric (NRD)-guide integrated circuits. On the basis of vertical modes in basis functions for NRD-guide circuits, vertical integration in space-domain is carried out analytically and a set of first-order Green's functions is constructed. Then, the solution of the volume integral-equation concerning with the NRD-guide circuits has been reduced to a two-dimensional planar problem in connection with each vertical mode. In this way, only the diagonal submatrices need to be calculated due to the orthogonal property of different vertical modes. A reduced calculation region technique is used for handling higher order vertical modes in which the fields are confined in the slot areas and their vicinities. The method was applied to a class of different hybrid structures. The results are in good agreement with measured results or the results obtained with other methods.     

A model for the computer-aided noise analysis of broad-banded bipolar circuits

A model suitable for the prediction of equivalent input noise voltage, equivalent input noise current, and noise figure of narrow geometry integrated bipolar devices is presented. The bipolar model accounts for flicker phenomena and the low frequency current gain attenuation commonly observed at very low and at very high injection levels. Moreover, a first-order approximation to the dependence of intrinsic base resistance on transistor current level is analytically incorporated. Experimental results are offered and compared with analytical estimates gleaned from a computer program written to output pertinent noise performance data for frequencies below the beta-cutoff frequency of a transistor.     

Manufacturing cost analysis of optoelectronic integrated circuits

A modified version of a recently proposed cost model for millimeter and microwave integrated circuits is applied to the cost analysis of optoelectronic integrated circuits. The particular example that is examined is a four-function receiver module for optical interconnects. On the basis of this analysis, it is concluded that the lowest receiver module cost, for any level of production, is achieved by integrating the receiver at the rate of two functions per chip, rather than a full single-chip integration of the receiver. This observation is the result of the loss of functional yield and a reduction of the number of die per wafer incurred by the increased die size