HEMT DCFL倒相器的模拟分析

目前,对HEMT逻辑单元电路的模拟分析基本上是基于SPICE模型,采用曲线拟合及参数提取等方法完成,较难从模拟结果直接获得有关器件物理参数与电路性能指标,给HEMT高速IC逻辑设计带来了困难。本研究进行了HEMT门特性的理论分析,提出了模拟HEMT DCFL倒相器直流传输特性及瞬态特性的新模型,并进行了计算机模拟。 在进行直流传输特性模拟时,讨论了电压传输过程中三个不同的工作区,利用K.Park提出的HEMT I—V特性模型,可得到各区输入与输出电压关系,即可完整地模拟出HEMT DCFL倒相器的直流传输特性,克服了C.H.Hyun模型中仅能模拟过渡区的缺陷。另外,还计算了负载管阈电压和源电阻对传输特性的影响。 Hyun简单地运用了导电机理不同于HEMT的GaAs无栅FET饱和电流表达式计算延迟时间,带来了一定的误差,本研究仍使用K.Park的I—V特性模型计算负载管导通电流,较为正确地计算出延迟时间与驱动管栅宽、负载管阈电压及电源电压的关系。 由于模型将器件的物理参数与电路性能指标有机结合,且较为全面地考虑了影响倒相器特性的诸因素,故较好地指导了HEMT IC的设计。     

1μm栅HEMT DCFL门电路及环形振荡器的设计与实验研究

利用作者提出的HEMT DCFL倒相器直流传输特性及瞬态特性计算机分析的模型,设计并制成了HEMT DCFL门电路及环形振荡器.在电路设计中,重点讨论了E/D NEMT倒相器的电路性能与器件的主要参数(栅长、栅宽、阈压)间的理论关系.工艺研究中,建立了挖栅时沟道饱和电流Is′与阈压值V_(t~h)间关系的理论曲线,并改进了传统化学湿法刻蚀工艺的阈压均匀性及E,D器件电流匹配的控制精度.实验制作了栅长为1μm的增强型和耗尽型HEMT.在1×1mm范围内,阈压偏差小于50mV,E/D倒相器的传输特性为:V_(OH)≈V_(DD),V_(OL)<0.1V,高、低电平转换范围仅0.1V,噪容达0.3V左右.研制的9级、17级环形振荡器,在V_(DD)为0.5V到3.5V范围内都观察到正弦波振荡波形.     

高压CMOS倒相器

本文介绍一种由高压PMOS器件作负载管和高压NMOS器件作驱动管的高压CMOS倒相器.这种倒相器的输入信号与TTL电平兼容,在50pf的负载下能成功地产生200V、1MH_z的高压脉冲,并能直接驱动等离子显示板或作高压功率开关.     

HEMT门特性分析及1μm栅单片HEMT IC的研制

<正> HEMT器件利用2DEG高迁移率的特点,在高速电路研制中具有很大潜力。尤其是采用E/D HEMT的DCFL逻辑电路,元件数少,工艺简单,可集中体现其高速、低功耗的特点。 进行了HEMT门特性的理论分析与计算机模拟,建立了使用E/DHEMT的DCFL门电路分析模型,并获得了与实验数据一致的分析结果。其直流传输特性曲线如图1所示。同时,开展了HEMT E/D倒相器、或非门(使用单栅HEMT)、与非门(使用双栅HEMT)及环形振荡器(包括9级、17级与19级)的实验研制,均取得较好结果。     

薄膜全耗尽SOI CMOS电路高温特性模拟和结构优化

在300～600K温度范围内,利用ISE TCAD模拟软件对全耗尽SOI电路的温度特性进行了模拟分析,得到了较全面的SOI CMOS倒相器静态特性和瞬态特性,并提出了一种改进的AlN-DSOI结构.结果显示,SOI CMOS电路的阈值电压对温度较为敏感,随着温度的升高,输出特性衰退明显.瞬态模拟也表明电路的速度和功耗受外界环境温度的影响较大.改进后的AlN-DSOI结构在有效缓解SOI结构热效应和浮体效应的基础上,显著提高了电路的速度和驱动能力.     

薄膜全耗尽SOI CMOS电路高温特性模拟和结构优化

在300～600K温度范围内,利用ISE TCAD模拟软件对全耗尽SOI电路的温度特性进行了模拟分析,得到了较全面的SOI CMOS倒相器静态特性和瞬态特性,并提出了一种改进的AlN-DSOI结构.结果显示,SOI CMOS电路的阈值电压对温度较为敏感,随着温度的升高,输出特性衰退明显.瞬态模拟也表明电路的速度和功耗受外界环境温度的影响较大.改进后的AlN-DSOI结构在有效缓解SOI结构热效应和浮体效应的基础上,显著提高了电路的速度和驱动能力.     

CMOS源极跟随缓冲电路

提出用 CMOS源极跟随缓冲电路以较少的电路段数快速驱动大电容负载 .HSPICE模拟结果表明 ,在负载电容为基本栅电容的 10 0倍及 6 0 0 0倍时 ,CMOS源极跟随缓冲电路具有高于多段倒相器缓冲电路的负载驱动能力 ,且占有面积小 .从而较好地解决了高速驱动芯片内各种数据传输及外部负载的问题 .该电路结构简单 ,易于实现 ,且制作工艺与标准 CMOS工艺完全兼容 .     

宽温区高温体硅CMOS倒相器的优化设计

在对体硅 CMOS倒相器直流特性、瞬态特性的高温模型和高温特性深入研究的基础上 ,提出了高温体硅 CMOS倒相器结构参数设计的考虑 ,给出了宽温区 (2 7～ 2 5 0℃ )体硅 CMOS倒相器优化设计的结果。模拟验证表明 ,所设计的体硅 CMOS倒相器在宽温区能满足下列电学参数设计指标 :输出高电平 Vo H>4 .95 V,输出低电平 Vo L<0 .0 5 V,转换电平 V*i (2 7℃ ) =2 .5 V,V*i(2 5 0℃ ) =2 .4 V,上升时间 tr(2 7℃ ) <110 ns,tr(2 5 0℃ ) <180 ns,下降时间 tf(2 7℃ ) <110 ns,tf(2 5 0℃ ) <16 0 ns。     

高温CMOS数字集成电路的瞬态特性分析

本文分析了高温CMOS倒相器和门电路的瞬态特性,建立了它们的上升时间,下降时间和延迟时间的计算公式。根据本文分析的结果,高温CMOS倒相器和门电路瞬态特性变差的原因是由于MOST阈值电压和载流子迁移率降低,以及MOST漏端pn结反向泄漏电流增大的缘故。本文给出的计算结果能较好地解释实验现象。     

MOS集成电路倒相器的特性分析

对金属-氧化物-半导体集成电路倒相器的直流电压传输特性和过渡特性进行了计算。为便于设计应用,结果用图表示出。讨论了传输门的过渡特性和倒相器的速度功耗乘积。     

Mixed-mode simulation of DX trap-induced slow transient effects onAlGaAs/GaAs HEMT inverters

A mixed level device and circuit simulation was performed to analyze DX trap-induced slow transient effects on the performance degradation of AlGaAs/GaAs high electron mobility transistor (HEMT) circuits. The variation of the output pulsewidth and the hysteretic characteristics of the input-output voltage transfer function in direct-coupled FET logic (DCFL) HEMT inverters have been simulated. In the model, a DX trap rate equation is calculated in the AlGaAs layer. The self-consistent Schrodinger and Poisson equations are solved numerically at each cross section of a device. A two-region Grebene-Ghandhi model is used to derive the I-V characteristics. The simulation confirms that the output pulse broadening and narrowing effects in string cascaded DCFL HEMT inverters are a consequence of the inverter voltage transfer function shift caused by deep traps     

Phase Noise Reduction of Microwave HEMT Oscillators Using a Dielectric Resonator Coupled by a High Impedance Inverter

The phase noise reduction in a configuration of the HEMT oscillator with a dielectric resonator coupled by a quarter‐wavelength impedance inverter is investigated. Two HEMT oscillators for a satellite payload system are manufactured in the same configuration except for the coupling configuration of the dielectric resonator (DR) in order to empirically demonstrate the phase noise reduction. Experimental result shows that a phase noise reduction by 14 dB can be enhanced by increasing the characteristic impedance of a coupling microstrip impedance inverter.     

Transient Modeling and Analysis of Pulse-Width Modulated Z-Source Inverter

The newly proposed Z-Source inverter has been proven in the literature to exhibit both steady-state voltage buck and boost capabilities using a unique LC impedance network coupled between the power source and converter circuit. This paper now presents transient modeling and analysis of a voltage-type Z-source inverter. These aspects are found to be challenging and they need to be carefully investigated before attempting to design advanced control algorithms for controlling the Z-source inverter. Through detailed analysis, the paper identifies several phenomena on the dc and ac-sides of the inverter, which would result in the inverter having a non-minimum-phase transient response. The dc-side phenomenon is associated with the Z-source impedance network, which is shown through small-signal and signal-flow-graph analyses to be having a right-half-plane zero in its control-to-output transfer function. Also, the ac-side phenomenon is shown through space vector analysis to depend on the time intervals of inverter states used for reconstructing the desired inverter output voltage. Based on the ac vectorial analysis, a method for improving the inverter transient response is also presented. Last, simulation results obtained using a switching-functional model and experimental results obtained using a laboratory prototype are presented for validating the described theoretical concepts     

Measurement and characterization of HEMT dynamics

The variation of high electron-mobility transistor (HEMT) large-signal behavior with a change in operating condition is examined with a view to understanding the dynamics involved and developing a modeling strategy. The observed variation exhibits the dynamics of thermal, impact ionization, and trapping effects. A novel measurement of drain characteristic transients gives time-evolution information that clearly shows these as separate quantifiable phenomena with significant dependence on initial operating conditions. A drain-current model that describes high-frequency characteristics with pinchoff, gain, and drain feedback parameters is adapted to describe the variation of the characteristics with changing operating conditions. The results reported give insight and grounding for simulation of HEMT circuits     

Calculator-aided design of MOS integrated circuits

A set of programs has been developed for the characterization of the d.c. and transient behavior of MOS integrated circuits. The d.c. analysis program calculates and plots the voltage transfer and power dissipation characteristic of a MOS inverter approached from a new point of view. The algorithm enables the characterization of basic MOS IC cells on desktop calculators. The program for the transient characterization calculates and plots the output waveform of three simple MOS cells most often occurring in MOS IC's.The MOS transistor is simulated in terms of a four-terminal large signal model described by device processing parameters. Complex MOS IC's can be also characterized by appropriate combining of these programs.     

Yield sensitivity of HEMT circuits to process parameter variations

The authors summarize the use of a graphical tool, yield factor histograms, to study the yield sensitivity of HEMT circuits to process parameter variations. A computer program called SPICENTER is used to incorporate the HEMT statistical physical model with a SPICE circuit model and then to generate the yield factor histograms and yield sensitivities as functions of the process parameters. The authors present the application of these tools to digital and microwave circuits. Two example HEMT circuits, a two-input NOR gate and an inverter chain, illustrate the concepts. Yield sensitivity is presented as yield percent change per parameter percent change     

Trapping Effects in the Transient Response of AlGaN/GaN HEMT Devices

In this paper, the transient analysis of an AlGaN/GaN high-electron mobility transistor (HEMT) device is presented. Drain-current dispersion effects are investigated when gate or drain voltages are pulsed. Gate-lag and drain-lag turn-on measurements are analyzed, revealing clear mechanisms of current collapse and related dispersion effects. Numerical 2-D transient simulations considering surface traps effects in a physical HEMT model have also been carried out. A comparison between experimental and theoretical results is shown. The presence of donor-type traps acting as hole traps, due to their low energy level of 0.25 eV relative to the valence band, with densities >1e20 cm^-3 (>5e12 cm^-2), uniformly distributed at the HEMT surface, and interacting with the free holes that accumulated at the top surface due to piezoelectric fields, accounts for the experimentally observed effects. Time constants next to 10 ms are deduced. Some additional features in the measured transient currents, with faster time constants, could not be associated with surface states     

基于PSCAD的逆变电路仿真

逆变电路的工作过程伴有电磁暂态过程,波形复杂且不便实际测量。利用电磁暂态分析软件PSCAD,建立了（PWM）控制方式的并联谐振型逆变电路的仿真模型,在此基础上进行了电路仿真和分析,仿真波形能准确地反映逆变电路的电磁暂态过程,证实了PSCAD软件在电力系统仿真领域比其他仿真软件更具优势。     

Characterization and improvement of GaAs HEMT analog switches forsampled-data applications

This paper presents design consideration and experimental comparison of GaAs HEMT analog switches for high-speed and high-precision sampled-data applications. At first, basic pass-transistor switches fabricated in a 0.5-μm GaAs HEMT technology are measured for characterization of transient errors induced due to clock-feedthrough and charge transfer. In order to improve the switch dynamic performances, a dual dummy transistor compensation technique is used and related driver circuitry is developed. On-wafer measurements demonstrate that the improved switch provides a significant reduction of the transient errors, a reasonable dynamic range, and a high isolation. The switch with a 0.53 pF load capacitor achieves a total harmonic distortion below -55 dB and -38 dB at 10 MHz and 1.0 GHz clock frequency, respectively