表面电场整形高压RESURF LDMOST

提出了采用对ＬＤＭＯＳ漂移区表面进行分段离子注入，对表面电场进行了整形的一种新结构高压ＲＥＳＵＲＦＬＤＭＯＳＴ。利用二维数值模拟对这种器件结构的分析表明，这种新结构显著降低了表面电场峰值，降低了采用ＲＥＳＵＲＦ技术导致的耐压对工艺参数变化的敏感性，并在耐压不降低的情况下缩短器件漂移区长度，得到低的比导通电阻Ｒｏｎ．Ａ。     

12-kV p-Channel IGBTs With Low On-Resistance in 4H-SiC

SiC bipolar devices are favored over SiC unipolar devices for applications requiring breakdown voltage in excess of 10 kV. We have designed and fabricated p-channel insulated-gate bipolar transistors (IGBTs) in 4H-SiC with 12-kV blocking voltage for high-power applications. A differential on-resistance of 18.6 $hbox{m}Omegacdothbox{cm}^{2}$ was achieved with a gate bias of 16 V, corresponding to a forward voltage drop of 5.3 V at 100 $ hbox{A/cm}^{2}$, indicating strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintaining a high carrier lifetime for conductivity modulation. The p-channel IGBT (p-IGBT) exhibits a transconductance that is $hbox{3}times$ higher than that of the 12-kV n-channel SiC IGBTs. An inductive switching test was done at 1.5 kV and 0.55 A $(sim !!hbox{140} hbox{A/cm}^{2})$ for the p-IGBTs, and a turn-on time of 40 ns and a turn-off time of $sim !!hbox{2.8} muhbox{s}$ were measured.      

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

A new superjunction LDMOS on silicon-on-insulator (SOI) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the high-density oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (BV). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to $hbox{6} times hbox{10}^{6} hbox{V/cm}$, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 $muhbox{m}$ and drift length of 15 $muhbox{m}$ on a thin SOI substrate.      

一种超低比导通电阻的L型栅漏极LDMOS

提出了一种具有超低比导通电阻的L型栅漏极LDMOS器件。该器件在两个氧化槽中分别制作L型多晶硅槽栅。漏极n型重掺杂区向下延伸,与衬底表面重掺杂的n型埋层相接形成L型漏极。L型栅极不仅可以降低导通电阻,还具有纵向栅场板的特性,可有效改善表面电场分布,提高击穿电压。L型漏极为电流提供了低阻通路,降低了导通电阻。另外,氧化槽折叠漂移区使得在相同耐压下元胞尺寸及导通电阻减小。二维数值模拟软件分析表明,在漂移区长度为0.9 μm时,器件耐压达到83 V,比导通电阻仅为0.13 mΩ·cm²。     

低比导通电阻P埋层SOI双介质槽MOSFET

提出了一种带P型埋层的新型SOI双介质槽MOSFET.通过在SOI层底部引入P型埋层作为补偿,在耐压优化情况下增加漂移区的浓度,降低了比导通电阻.MEDICI TCAD仿真结果表明:在281 V击穿电压下,该结构的比导通电阻为4.6 mΩ·cm2,与不带P型埋层的结构相比,在达到同样耐压的情况下,比导通电阻降低了19％.     

Suppression of Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-Plate Structure

The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the gate and drain as a result of using the dual FP. The gate-drain charge Q _gd for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Q _gd /A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, R _on A was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, R _on Q _gd for 600-V device was reduced to 0.32 OmeganC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability.     

一种用于高压防护的新型闩锁免疫LDMOS

横向双扩散MOSFET(LDMOS)由于其高击穿电压特性而被认为是适合在高压中应用的防止静电放电(ESD)现象的保护器件.在传统结构中,LDMOS的鲁棒性相对较差,这是器件自身固有的不均匀导通特性和Kirk效应导致的.可将可控硅整流器(SCR)嵌入到LDMOS结构(即NPN_LDMOS)中.然而,SCR固有的正反馈效应...     

一种适用于高压集成电路的新型LDMOS器件

高压集成电路是将高压器件和低压控制电路集成在同一芯片上的集成电路，高压集成电路的研究与发展，主要是高压器件、高压集成电路工艺以及设计技术的发展。文章提出了一种适用于高压集成电路的新型LDMOS器件，并对该器件结构进行了耐压分析，给出了该器件的击穿特性；等势线和电流线等模拟曲线。对不同参数模拟的曲线进行了分析和比较。结果表明，该结构具有比较高的击穿电压，并且工艺简单，受工艺参数波动的影响较小，不失为一种提高集成电路耐压的新途径。     

PDP驱动芯片中高压LDMOS建模

建立了PDP驱动芯片用高压LDMOS的SPICE子电路模型,该模型集成了LDMoS固有特性:准饱和特性、电压控漂移区电阻、自热效应、密勒电容等.与其他物理模型和子电路模型比较,该模型不但能提供准确的模拟结果,而且建模简单快捷,另外该模型可较容易地嵌入SPICE模拟软件中.模型的实际应用结果显示:模拟与实测结果误差在5%以内.     

PDP驱动芯片中高压LDMOS建模

建立了PDP驱动芯片用高压LDMOS的SPICE子电路模型,该模型集成了LDMOS固有特性：准饱和特性、电压控漂移区电阻、自热效应、密勒电容等. 与其他物理模型和子电路模型比较,该模型不但能提供准确的模拟结果,而且建模简单快捷,另外该模型可较容易地嵌入SPICE模拟软件中. 模型的实际应用结果显示：模拟与实测结果误差在5%以内.     

A High-Voltage ZVZCS DC--DC Converter With Low Voltage Stress

A high-voltage zero-voltage-zero-current-switched dc--dc converter with low voltage stress is presented in this paper. Its circuit structure is extended from a previously developed zero-voltage-switched dc--dc converter consisting of six series-connected switching devices, one three-phase transformer, and an output current tripler. The voltage stress on each switching device is only one-third of the input voltage. Compared with the previous converter, apart from retaining the advantage of having low voltage stresses on the switches, the main advancements of the proposed converter have also included 1) wider soft-switching range; 2) elimination of circulating energy on the primary side during the freewheeling stage; and 3) use of phase-shift pulsewidth modulation in output voltage control. Detailed topological operations and steady-state characteristics of the converter will be given. A 2.2-kW, 990-V/110-V dc--dc converter prototype has been built and tested. Experimental results are favorably compared with the theoretical predictions.      

AlGaN/GaN Dual-Channel Lateral Field-Effect Rectifier With Punchthrough Breakdown Immunity and Low On-Resistance

We propose an AlGaN/GaN dual-channel lateral field-effect rectifier (DCL-FER) with improved balance between the reverse breakdown voltage (BV) and on-resistance. Instead of utilizing a long single enhancement-mode (E-mode) Schottky-controlled channel to enhance the punchthrough BV but inevitably sacrifice the on-resistance, the DCL-FER features a dual channel consisting of one E-mode section and one depletion-mode (D-mode) section in series. The D-mode channel provides higher carrier density that facilitates high on-current or low on-resistance while still preventing the E-mode channel from being punched through under high reverse voltage. For rectifiers with the same physical dimensions (a drift region length of 5 ?m and a Schottky-controlled channel length of 2 ?m), the DCL-FER is shown to deliver comparable BV while featuring 53% lower on-resistance.     

一种LDMOS高压运算放大器的设计与实现

使用专门设计的LDMOS高压器件,实现了一个具有高压驱动能力(±150 V)和大增益(>80 dB)的CMOS运算放大器。模拟结果显示,N沟道和P沟道LDMOS晶体管的最大击穿电压都超过了320 V,高压隔离超过300 V,从而可以确保其高压放大功能。该运算放大器适用于数字通信,如程控交换机中的高压驱动电路的单片集成。     

可变低k介质层SOI LDMOS高压器件的耐压特性

提出了一种可变低κ（相对介电常数）介质层（variable low κ dielectric layer，VLkD）SOI高压器件新结构，该结构的埋层由可变κ的不同介质组成。基于电位移连续性原理，利用低κ提高埋层纵向电场和器件纵向耐压，并在此基础上提出SOI的介质场增强原理，基于不同κ的埋层对表面电场的调制作用，使器件横向耐压提高，并给出VLkD SOI的RESURF判据，借助2D器件仿真研究了击穿特性与VLkD SOI器件结构参数之间的关系，结果表明，对κμ=2，κIH=3．9，漂移区厚2μm，埋层厚1μm的VLkD器件，埋层电场和器件耐压分别达248V／μm和295V，比相同厚度的常规SOI器件的埋层电场和耐压分别提高了93％和64％。     

带p埋层表面注入硅基LDMOS模型与优化

提出一种带p埋层的表面注入硅基LDMOS高压器件新结构,称为BSI LDMOS(surface implanted LDMOS with p buried layer).通过表面注入n+薄层降低导通电阻,p埋层不但改善横向表面电场分布,提高击穿电压,而且增大漂移区优化浓度.求解电势的二维Poisson方程,获得表面电场和击穿电压的解析式,研究结构参数对表面电场和击穿电压的影响,数值与解析结果吻合较好.结果表明:与常规结构相比较,BSI LDMOS大大改善了击穿电压和导通电阻的折衷关系.     

带p埋层表面注入硅基LDMOS模型与优化

提出一种带p埋层的表面注入硅基LDMOS高压器件新结构,称为BSI LDMOS(surface implanted LDMOS with p buried layer).通过表面注入n 薄层降低导通电阻,p埋层不但改善横向表面电场分布,提高击穿电压,而且增大漂移区优化浓度.求解电势的二维Poisson方程,获得表面电场和击穿电压的解析式,研究结构参数对表面电场和击穿电压的影响,数值与解析结果吻合较好.结果表明:与常规结构相比较,BSI LDMOS大大改善了击穿电压和导通电阻的折衷关系.     

可变低k介质层SOI LDMOS高压器件的耐压特性

提出了一种可变低k(相对介电常数)介质层(variable low k dielectric layer,VLkD)SOI高压器件新结构,该结构的埋层由可变k的不同介质组成.基于电位移连续性原理,利用低k提高埋层纵向电场和器件纵向耐压,并在此基础上提出SOI的介质场增强原理.基于不同k的埋层对表面电场的调制作用,使器件横向耐压提高,并给出VLkD SOI的RESURF判据.借助2D器件仿真研究了击穿特性与VLkD SOI器件结构参数之间的关系.结果表明,对kIL=2,kIH=3.9,漂移区厚2μm,埋层厚1μm的VLkD器件,埋层电场和器件耐压分别达248V/μm和295V,比相同厚度的常规SOI器件的埋层电场和耐压分别提高了93%和64%.     

可变低k介质层SOI LDMOS高压器件的耐压特性

提出了一种可变低k(相对介电常数)介质层(variable low k dielectric layer,VLkD)SOI高压器件新结构,该结构的埋层由可变k的不同介质组成.基于电位移连续性原理,利用低k提高埋层纵向电场和器件纵向耐压,并在此基础上提出SOI的介质场增强原理.基于不同k的埋层对表面电场的调制作用,使器件横向耐压提高,并给出VLkD SOI的RESURF判据.借助2D器件仿真研究了击穿特性与VLkD SOI器件结构参数之间的关系.结果表明,对kIL=2,kIH=3.9,漂移区厚2μm,埋层厚1μm的VLkD器件,埋层电场和器件耐压分别达248V/μm和295V,比相同厚度的常规SOI器件的埋层电场和耐压分别提高了93%和64%.     

高压RESURF LDMOST的开态电阻与关态电压

降低表面电场原理可大大提高ＬＤＭＯＳＴ的器件性能。本文详细研究了用ＲＥＳＵＲＦ原理设计的ＬＤＭＯＳＴ的开态电阻与击穿电压的理论分析模型，并根据这一模型对ＲＥＳＵＲＦ ＬＤＭＯＳＴ的优化设计深入的讨论。最后评价了高压ＲＥＳＵＲＦ ＬＤＭＯＳＴ在保持器件耐压不变时降低其开态电阻的几种方法。     

用阱作高阻漂移区的LDMOS导通电阻的解析模型

分析了一个用阱作为耐高压漂移区的LDMOS的导通电阻,提出了带有场极板的高阻漂移区导通电阻的计算公式,改进了双扩散沟道导通电阻的计算公式.针对一个LDMOS的例子做了计算,并将其与相同参数情况下用MEDICI软件模拟的结果作了对比.结果表明两者相差仅5％,这说明所得公式可用于该类型LDMOS的分析和设计.