共查询到19条相似文献,搜索用时 203 毫秒
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深亚微米CMOS运算放大器的综合 总被引:5,自引:1,他引:5
利用一种计算电路直流工作点的技术,并采用基于BSIM3v3M OS模型的MOS管评估器来提高基于公式法进行电路综合的精度;同时提出一种综合策略,使得综合后得出的运算放大器在工艺波动和工作条件(如电源电压和温度)变化时,仍能满足性能要求.大量的实验结果表明:文中方法可以快速综合出可制造的深亚微米CMOS运算放大器. 相似文献
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基于多阈值技术的超低功耗电路设计 总被引:1,自引:0,他引:1
随着工艺进入深亚微米阶段,漏电流带来的静态功耗已经成为不可忽视的部分。多阈值CMOS技术是一种降低电路漏电流功耗的有效方法。本文在延迟不敏感异步电路中应用多阈值CMOS技术,该设计能显著的降低功耗,同时解决了同步电路存在的问题,比如sleep信号的产生,存储元件在sleep模式下数据丢失。这对深亚微米低功耗电路的设计具有一定的实际意义。 相似文献
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FDAADS系统中模拟CMOS单元电路的自动综合 总被引:3,自引:3,他引:0
介绍了一种基于优化的CMOS单元电路的自动综合方法,该方法利用一种新颖的电路性能评估技术来缩短综合软件的运行时间、提高设计精度,此外,采用模拟退火法优化算法进行求解,并结合一些其它方法来提高获得全局优化解的能力,利用上述方法实现的一些CMOS单元电路的自动综合模块已经集成到FDAADS-“复旦模拟电路自动化设计系统”中,大量的实验结果表明:上述方法可以用较少的时间产生高精度的设计结果。 相似文献
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对称三值逻辑及对称三值CMOS电路 总被引:6,自引:0,他引:6
本文从负数表示的研究引入对称三进制系统与对称三值逻辑.基于作者提出的传输函数理论,本文讨论了基本对称三值运算的CMOS电路实现,并已用计算机模拟证明它们具有正确的逻辑功能与理想的DC传输特性.基于这些基本电路单元,本文进一步设计了实现加法与乘法的两种对称三值运算单元. 相似文献
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运算放大器(OPERATIONAL AMPLIFIER)是模拟电路中最重要和最通用的单元电路之一。基于0.5 umCMOS混合工艺设计了一种三级CMOS运算放大器,它具有放大倍率高,静态功耗低,适合大规模集成等特点。 相似文献
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使用同步电路综合工具优化异步电路 总被引:1,自引:0,他引:1
现可用的同步电路综合工具对捆绑数据类异步电路直接映射的方法不能有效地约束时序,分模块综合的方法不能进行全局优化,其中以标准单元组成C单元降低了电路性能、增加了电路面积.通过将4相位捆绑数据寄存器流水线数据通道等效为一个同步流水线,可以自顶向下地进行有时序约束的综合,采用全定制C单元,并把其当作组合逻辑门进行分析,综合出的电路更加优化.使用此方法实现的一个数据流AES芯片的数据通道的面积延时积是直接映射方法的88%左右,实际芯片的整体性能优于一个由Balsa实现的AES芯片。 相似文献
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深亚微米工艺使SoC芯片集成越来越复杂的功能,测试开发的难度也不断提高。由各种电路结构以及设计风格组成的异构系统使测试复杂度大大提高,增加了测试时间以及测试成本。描述了一款通讯基带SoC芯片的DFT实现,这款混合信号基带芯片包含模拟和数字子系统,IP核以及片上嵌入式存储器,为了满足测试需求,通过片上测试控制单元,控制SoC各种测试模式,支持传统的扫描测试以及专门针对深亚微米工艺的,操作在不同时钟频率和时钟域的基于扫描的延迟测试模式,可配置的片上存储器的BIST操作以及其它一些特定测试模式。 相似文献
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Kai Huang Luca Santinelli Jian-Jia Chen Lothar Thiele Giorgio C. Buttazzo 《Real-Time Systems》2011,47(2):163-193
Power dissipation has been an important design issue for a wide range of computer systems in the past decades. Dynamic power
consumption due to signal switching activities and static power consumption due to leakage current are the two major sources
of power consumption in a CMOS circuit. As CMOS technology advances towards deep sub-micron domain, static power dissipation
is comparable to or even more than dynamic power dissipation. This article explores how to apply dynamic power management
to reduce static power for hard real-time systems. We propose online algorithms that adaptively control the power mode of
a system, procrastinating the processing of arrived events as late as possible. To cope with multiple event streams with different
characteristics, we provide solutions for preemptive earliest-deadline-first and fixed-priority scheduling policies. By adopting
a worst-case interval-based abstraction, our approach can not only tackle arbitrary event arrivals, e.g., with burstiness,
but also guarantee hard real-time requirements with respect to both timing and backlog constraints. We also present extensive
simulation results to demonstrate the effectiveness of our approaches. 相似文献
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为了兼顾模拟集成电路设计优化的求解精度和计算效率,提出一种基于正项式模型修正技术的几何规划优化方法.首先将模拟集成电路的设计目标与约束简化为正项式模型,然后在采用几何规划方法迭代优化的过程中利用晶体管级SPICE仿真不断修正这一正项式模型.实例表明,与传统基于公式的优化方法和基于仿真的优化方法相比,该方法能够在尽量保证计算效率和全局最优解的前提下使优化精度满足晶体管级SPICE仿真的要求. 相似文献
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随着深亚微米技术的发展,功耗已经成为现代超大规模集成电路设计中的一个主要设计约束.本文在设计多点控制协议MPCP模块中,采用插入门控时钟这一技术以降低芯片功耗.针对插入门控寄存器造成测试很难控制这个问题,采取在锁存器的前后加入控制点的方法,解决了由于插入门控时钟而对可测性造成的影响.最后,使用SMIC的0.25um CMOS工艺,并用Synopsys的power complier进行功耗优化,达到了很好的效果. 相似文献
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This paper presents a new approach for detecting defects in analog integrated circuits using a feed-forward neural network
trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting faults in
a simple analog CMOS circuit by representing the differences observed in power supply current of fault-free and faulty circuits.
The identification of defects was performed in time and frequency domains, followed by a comparison of results achieved in
both domains. We show that resilient back-propagation neural networks can be a very efficient and versatile approach for identifying
defective analog circuits. Moreover, this approach is not limited to the supply current analysis, because it also offers monitoring
of other circuit parameters. The type of defects detected by the resilient backpropagation neural networks, as well as other
possible applications of this approach, are discussed. 相似文献
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A new four-quadrant CMOS analog multiplier is presented, based on devices operating in the subthreshold mode of conduction. The proposed circuit is a cross-coupled quad structure in which differential multiplication is obtained by driving the gate and bulk (back gate) terminals of the devices. Analysis and simulation have shown that the new structure has the characteristics required for the design of very large scale integration (VLSI) analog neural networks. Although operating at subthreshold current levels, reasonable speed can be obtained since voltage swings are in the range of a few V(t). The behavior of the basic multiplier has been assessed experimentally using transistor-arrays and simulation studies on a network including 11 neurons and 31 synapses indicate a useful level of functionality. 相似文献
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Ultraviolet (UV) photoinjection of electrons through SiO(2 ) provides a convenient and simple method for programming analog, nonvolatile memories in CMOS circuits. The time scales involved in the UV programming process are well suited to multiple time scale learning algorithms providing several orders of magnitude in programming rate. The method requires no special processing technology. Measured characteristics of the UV photoinjection devices and experimental results from a synapse circuit built using these devices are presented. This synapse circuit includes a continuously adjustable weight, an electronic learn/hold control and slow forgetting dynamics, while allowing an unimpeded multiplication operation at all times. 相似文献
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在高速串行接口芯片的设计中,高速串行数据恢复电路是设计中的一个难点,由于其高达千兆的传输频率,大多采用模拟电路方式实现·然而同数字电路相比,模拟电路在噪声影响、面积、功耗、工艺敏感度和可测性方面都存在较大的劣势·提出了一个应用于SATA1·0中1·5Gbps高速串行接口的高速串行数据恢复电路,它没有用PLL或DLL等模拟电路的方法,它采用完全数字电路的设计,并用标准单元实现·与用模拟电路实现的串行数据恢复电路相比,此电路设计更加简单易实现,数据恢复快速,而且面积小功耗低·电路被应用在PATA/SATA桥接芯片的设计中,并在标准0·18CMOS工艺下投片生产· 相似文献