CMMB系统中LDPC码研究和性能分析

LDPC码是一种已被证明可接近香农极限的信道编码技术。该文研究了中国移动多媒体广播系统（China Mobile Multimedi aBroadcasting,CMMB）中的LDPC码结构特点,并且采用LU分解编码算法和BP译码算法在AWGN信道中进行了仿真。仿真结果表明,LDPC应用于CMMB系统中极大地提高了系统...     

基于CMMB的外辐射源雷达信号模糊函数分析与处理

根据中国移动多媒体广播(CMMB)信号结构,该文分析了该信号作为雷达辐射源的模糊函数特性,研究了副峰产生的机理,并与欧洲数字视频地面广播(DVB-T)信号特性做了比对;针对因循环前缀引起的模糊函数副峰和同步信号引起的多普勒模糊带对目标探测产生的不利影响,提出了副峰抑制的方法。仿真和实测结果验证了文中副峰产生机理分析的正确性,同时所采用的方法能有效抑制模糊副峰,为目标探测奠定了基础。     

基于FPGA的部分并行QC-LDPC译码器高效存储方法

针对部分并行结构的准循环低密度校验(QC-LDPC)码译码器,提出了一种将译码准码字存储在信道信息和外信息存储块中的高效存储方法,该方法不需要额外的存储块来存储译码准码字,能够减少译码器实验所需的存储资源数量,并且有效降低了译码电路的布线复杂度.在Xilinx XC2V6000-5ff1152 FPGA上的实验结果表明,提出的QC-LDPC码译码器设计方法能够在降低系统的BRAM资源需求量的同时有效地提高系统的运行频率和译码吞吐量.     

中国移动多媒体广播外辐射源雷达参考信号获取方法研究

该文结合中国移动多媒体广播(CMMB)信号的特殊结构,提出了两种CMMB外辐射源雷达参考信号获取方法,即基于CMMB同步信号的自适应滤波提纯算法与利用CMMB调制解调理论的参考信号重构算法。首先给出了两种算法的具体处理流程;接着通过计算机仿真重点分析比较了两种算法的性能,利用实测处理验证了重构算法的有效性。研究表明基于参考信号重构的提纯方法能有效地消除参考信号中的噪声干扰和多径干扰,具有获取参考信号纯度高、算法稳健等优点。     

在CMMB系统中提高接收性能的AGC方法

文中针对移动数字多媒体广播多时隙的特点,提出了一种全新的自动增益控制（AGC）方法。根据采样得到的多媒体广播的当前信号平均功率,将增益控制信号反馈给自动增益控制电路,即重新设置Tuner的增益。如果当前信号平均功率大于设定的接收信号功率范围,则减小Tuner的增益,否则增大Tuner的增益,最终将接收到的信号平均功率调整到设定的范围内,以便接收终端能够流畅的接收播放移动多媒体广播的音视频信号、紧急广播信息以及播发的其它信息。     

中国移动多媒体广播外辐射源雷达相干积累的非均匀采样实现

中国移动多媒体广播(CMMB)与欧洲数字视频地面广播(DVB-T) 的信号结构有显著区别,使得CMMB外辐射源雷达信号处理方法和实时并行计算面临一些新问题。该文针对CMMB信号的特殊结构,提出了一种易于并行实现的非均匀采样相干积累方法。首先阐述了算法的内在机理和处理流程,接着分析了该方法的分辨率与主旁瓣性能,最后通过实测数据处理验证了所提方法的有效性。     

Area-efficient analog decoder design for low density parity check codes in deep-space applications

Area-efficient design methodology is proposed for the analog decoding implementations of the rate-½ accumulate repeat-4 jagged-accumulate (AR4JA) low density parity check (LDPC) code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verify the approach is fully integrated in a four-metal double-poly 0.35 μm complementary metal oxide semiconductor (CMOS) technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm² with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable for space- and power-constrained spacecraft system.     

A new generation of modems for power efficient radio systems

A new class of generalized intersymbol-interference and jitter-free (GIJF) modulated signals is introduced. Computer simulation and hardware experimental research results demonstrate that our proposed new generation of signals and modulators leads to significant performance improvements in non-linearly amplified broadband radio systems. For increased power efficiency, non-linear amplification is required in most commercial satellite and terrestrial microwave systems. In particular, we demonstrate that the 3 dB envelope fluctuation of currently used offset raised-cosine overlapped QPSK systems is reduced to 0-5 dB, and that the BER performance is improved by approximately 1 dB. These significant technical performance advantages are expected to lead to more economical implementations of digital transmission systems.     

一种适用于概率LDPC译码器的双路更新边缘存储器

针对采用传统边缘存储器结构的概率低密度奇偶校验(Low Density Parity Check,LDPC)译码器中仍存在锁存问题的现象,借鉴全并行Turbo译码器中的多路更新策略,提出了一种增强的变量节点和校验节点双路更新边缘存储器结构。利用双路更新结构引入的增强随机选择特性,可以显著降低概率迭代译码过程中的锁存现象。仿真分析表明,相比于单路更新结构,采用双路更新边缘存储器结构的概率LDPC译码器能够在误比特率接近10-4量级处获得0.4 dB左右的译码性能增益,同时也能够显著降低迭代译码周期数量,提升译码速率。     

An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications

In this paper, an area efficient and high throughput multi-rate quasi-cyclic low-density parity-check (QC-LDPC) decoder for IEEE 802.11n applications is proposed. An overlapped message passing scheme and the non-uniform quantization scheme are incorporated to reduce the overall area and power of the proposed QC-LDPC decoder. In order to enhance the decoding throughput and reduce the size of memories storing soft messages, an improved early termination (ET) scheme and base matrix reordering technique is employed. These techniques significantly reduce the total number of decoding iterations and memory accessing conflicts without mitigating the decoding performance. Equipped with these techniques an area efficient and high throughput multi-rate QC-LDPC decoder is designed, simulated and implemented with Xilinx Virtex6 (XC6VLX760-2FF1760) for an irregular LDPC code of length 1944 and code rates (1/2–5/6) specified in IEEE 802.11n standard. With a maximum clock frequency of 574.136–587.458 MHz the proposed QC-LDPC decoder can achieve throughput in the range of 1.27–2.17 Gb/s for 10 decoding iterations. Furthermore, by using Cadence RTL compiler with UMC 130 nm VLSI technology, the core area of the proposed QC-LDPC decoder is found to be 1.42 mm² with a power dissipation in the range of 101.25–140.42 mW at 1.2 V supply voltage.     

High performance parallel turbo decoder with configurable interleaving network for LTE application

In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving. This 2ⁿ-input network can be configured to support any 2ⁱ-input $(0\le i\le n)$ network. Furthermore, it can flexibly support arbitrary contention-free interleavers by cascading an additional specially designed network. In addition, an optimized decoding schedule scheme is presented to reduce the performance loss caused by high parallelism. Memory architecture and address mapping method are optimized to avoid memory access contention of small blocks. Moreover, a dual-mode add–compare–select (ACS) unit implementing both radix-2 and radix-4 recursion is proposed to support the block sizes that are not divided by 16. Implemented in 130 nm CMOS technology, the design achieves 384.3 Mbps peak throughput at clock rate of 290 MHz with 5.5 iterations. Consuming 4.02 mm² core area and 716 mW power, the decoder has a 1.81 bits/cycle/iteration/mm² architecture efficiency and a 0.34 nJ/bit/iteration energy efficiency, which is competitive with other recent works.     

一种用于T-DMB系统IP业务传输的GSE-FEC方案

该文采用通用流封装GSE来完成地面数字多媒体广播(T-DMB)系统的IP业务的传输,提出了一种改进的GSE-FEC方案。其中设计了一种可提供帧重构信息以及错误位置信息的改进的GSE封装(IGSE),进一步提出了基于IGSE的带擦除译码方案IGE,用于GSE-FEC方案的译码部分, 较好地提高了GSE-FEC的性能。仿真结果表明,IGE与基于非带擦除(NE)以及基于现有GSE封装的带擦除(GE)RS译码方案相比,均表现出更强的纠错能力,另外,与GE方案相比,IGE可以更好的保护正确字节,有效的减少信息浪费。     

累加交叉并行级联单奇偶校验码的低复杂度译码算法

累加交叉并行级联单奇偶校验(A-CPSPC)码是一种新的纠错编码,其编码结构简单并具有较好的误比特率性能。该文针对A-CPSPC码的局部编码结构提出了一种低复杂度的最大后验(MAP)局部译码算法,该方法利用基于双向消息传递原则的和积算法(SPA)进行局部译码,消除了短环对局部译码性能的影响。分析及仿真表明,传统的置信传播算法并不适用于A-CPSPC码,该文提出的局部译码算法与基于BCJR算法的局部译码算法的性能一致,且复杂度更低。     

一种高速长距离光通信系统中QC-LDPC码的构造方法

提出了一种新的准循环低密度奇偶校验(QC-LDPC)码的构造方法,给出了用该方法构造无环四QC-LDPC码的充分条件。并针对光通信系统的传输特点,用此方法构造了适用于高速长距离光通信系统的QC-LDPC(4 221,3 956)码。仿真结果分析表明:在码率为93.7%、误码率BER为10-6时,与广泛用于光通信系统中的经典RS(255,239)码相比,其净编码增益(NCG)提高了约1.8dB;比SCG-LDPC(3 969,3 720)码的NCG提高了约0.2dB,距离香农极限约1.4dB,且远低于PEG-LDPC(4 221,3 956)码的错误平层,这正满足光通信系统中低错误平层的要求。     

DTMB标准中BCH译码算法及其FPGA的实现

首先证明了DTMB标准中采用的BCH码是纠错能力为1的循环汉明码,并基于此提出了适用于该BCH码的译码算法,及其串行和并行两种FPGA实现电路。考虑到该BCH码缩短码的特性,通过修改差错检测电路,使其译码时延缩短34%。实现结果表明,译码器译码正确无误,FPGA资源占用极少。串行译码器总时延为762个时钟周期,最大工作时钟频率可达357MHz。并行译码器总时延仅为77个时钟周期,最大工作时钟频率可达276MHz。     

一种用于BICM-ID系统的新颖8APSK映射方案

为了能够通过高阶调制信号增加信道容量,提高编码增益和频谱效率,对8阶振幅移相键控(APSK)星座映射方案进行优化.基于欧氏距离设计准则提出一种新颖(2,6)-scheme 8APSK映射方案,并应用于联合准循环构造法构造的低密度奇偶校验(LDPC)(4599,4307)码的比特交织编码调制迭代译码(BICM-ID)系统中.信道容量仿真表明,所提方案在高、低信噪比区域都具有非常优越的互信息性能.误码率(BER)性能仿真表明,在BER为10-7时,联合LDPC(4599,4307)码的(2,6)-scheme 8APSK映射方案较(4,4)-scheme 8APSK映射方案、8PSK调制的格雷(Gray)映射、集分割(SP)映射、半集分割(SSP)映射分别提高了约0.45 dB、1.10 dB、1.62 dB、2.13 dB的编码增益.外附信息转移(EXIT)图仿真说明,所提方案能够更早地打开译码通道,从而更早地通过迭代来实现无错译码.     

基于改进罚函数的LDPC码分层调度ADMM惩罚译码

通过增加伪码字的代价,基于交替方向乘子法（Alternating Direction Method of Multipliers,ADMM）的惩罚译码方法可以改善低密度奇偶校验（Low-Density Parity-Check,LDPC）码低信噪比区域的译码性能,同时具有低的译码复杂度.而减少ADMM惩罚译码的欧几里德投影次数、选择合适的消息调度策略和设计有效的罚函数是提高ADMM惩罚译码速度的三种重要方法.为了进一步提高ADMM惩罚译码速度,通过利用Wei等人提出的方法来减少欧几里德投影的次数,本文设计了基于I-l₁-PF罚函数的水平分层调度与垂直分层调度策略的两种LDPC码ADMM惩罚译码方法.仿真实验表明,与现有ADMM惩罚译码方法相比较,所设计的译码方法不仅具有较好的译码性能,而且能够显著降低LDPC码译码的平均迭代次数和平均译码时间.     

一种引入积分修正的二维信息大数逻辑LDPC译码算法

为了解决基于可靠度的迭代大数逻辑译码(Modified Reliability-based Iterative Majority Logic Decoding, MRBI-MLGD)算法的错误平层问题,提出了一种基于大数逻辑的低密度奇偶校验(Low Density Parity Check, LDPC)译码算法。所提算法在译码函数中引入积分修正项,实现了基于二维信息修正的译码策略,可有效降低错误平层。此外,与基于二元译码信息的的迭代大数逻辑译码(Binary Message Majority Logic Decoding, BM-MLGD)算法不一样,所提算法可适用于不同列重的LDPC码。仿真结果表明,所提译码算法在整个工作信噪比区间内都具有稳定的译码性能,表现出更好的普适性和鲁棒性。     

An efficient approximate maximum likelihood signal detection for MIMO systems

This paper proposes an efficient approximate Maximum Likelihood （ML） detection method for Multiple-Input Multiple-Output （MIMO） systems, which searches local area instead of exhaustive search and Selects valid search points in each transmit antenna signal constellation instead of all hyperplane. Both of the selection and search complexity can be reduced significantly. The method performs the tradeoff between computational complexity and system performance by adjusting the neighborhood size to select the valid search points. Simulation results show that the performance is comparable to that of the ML detection while the complexity is only as the small fraction of ML.