The $hbox{1}/f$ Noise and Random Telegraph Noise Characteristics in Floating-Gate nand Flash Memories

We have characterized low-frequency noise (LFN) such as $hbox{1}/f$ noise and random telegraph noise (RTN) in a nand Flash memory cell string for the first time and shown its fundamental properties. The nand Flash memory cells showed specific LFN characteristics under various conditions such as bit-line bias, word-line bias of a selected cell, and pass bias of the unselected cells in the nand string. Also, LFN was investigated with the program/erase (P/E) cycling of a cell or all cells in a string, and maximum threshold voltage fluctuation of several tens of millivolts after $sim$100 000 cycles at the 70-nm technology node was shown. Finally, we predicted the effects of LFN in sub-70-nm nand Flash memories.      

Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

This letter demonstrates a novel twin poly-Si thinfilm transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after $hbox{10}^{3}$ P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.      

Discrete Dopant Effects on Statistical Variation of Random Telegraph Signal Magnitude

This paper discusses the discrete channel dopant effects on the statistical variation of random telegraph signal (RTS) magnitude, which is defined by the threshold-voltage shift by RTS in MOSFETs. An analytical model for the statistical variation of RTS magnitude is presented. Considering discrete dopant effects, the RTS magnitude of MOSFETs exhibits a log-normal distribution, while the threshold voltage itself exhibits a normal distribution. The threshold-voltage shift by RTS will become a serious concern in 50-nm Flash memories and beyond.     

Carbon-Doped Polysilicon Floating Gate for Improved Data Retention and P/E Window of Flash Memory

We propose a novel approach to engineering floating gates (FGs) of Flash memory cells, namely, carbon incorporation into polysilicon FGs. This technique demonstrated an improvement in retention and a larger program/erase $V_{t}$ window, particularly for smaller capacitance coupling ratio cells, which is important for future scaled Flash memory cells.      

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

An asymmetric two-side program with one-side read (ATPOR) device for MultiBit per cell MLC nitride-trapping flash memories

An asymmetric two-side program with one-side read (ATPOR) Flash memory device is proposed. In this nitride-trapping device, the interaction of stored charges in the two sides (second-bit effect) is utilized to achieve multilevel cell (MLC) V/sub t/ levels with the advantages of relatively small total charge. The small total charge can enhance both programming and erasing efficiency. The ATPOR device with programming and erasing times within 100 ns and 40 /spl mu/s are demonstrated. Excellent read disturb immunity of ATPOR device can provide high scaling capability. In addition, good data retention and P/E cycling endurance and reliability are achieved. For 2-bit/cell and 3-bit/cell MLC applications, the ATPOR device with tight level distributions less than 100 mV is illustrated.     

Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation

The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.     

Flash memory goes mainstream

The operation of the flash memory, which has matured over the last five years from a novelty product, is described. Both dual and single supply voltage devices are considered. Flash memory cycling, data reliability, program/erase algorithms, and blocking are discussed. Three approaches to flash memories are examined. The uses of these devices and some new architectures are considered     

Flash memory reliability

With reference to the mainstream technology, the most relevant failure mechanisms which affect yield and reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The effectiveness of a good test methodology combined with a proper product design for screening at wafer sort latent defects of tunnel oxide is highlighted as a key factor for improving Flash memory reliability. The degradation of device performance induced by program/erase cycling is discussed, covering both the behaviour of a typical cell and the evolution of memory array distribution. The erratic erasure phenomenon is illustrated as the most relevant mechanism reported so far to cause single bit failures in endurance tests. Finally, reliability implications of multilevel cell concepts are briefly analysed.     

On the RTS phenomenon and trap nature in Flash memory tunnel oxide

Aim of this work is the investigation of Random Telegraph Signal (RTS) in Flash memory cell. Current fluctuations have been performed also as a function of temperature in order to characterize the nature of traps responsible for noise in relatively thick tunnel oxide. Trap energy level and spatial localization from the Si/SiO₂ interface has been determined. The impact of stress has been also investigated showing no significant noise increase in single cell. This has been ascribed to the tunnel oxide technology whose heavy nitridation allows minimizing the degradation of the region responsible for RTS in Flash memory cell.     

Random telegraph signal currents and low-frequency noise injunction field effect transistors

The detailed study of random telegraph signal (RTS) currents and low-frequency (LF) noise in semiconductor devices in recent years has confirmed their cause and effect relationship. In this paper we describe the physical mechanisms responsible for RTS currents in any device. The methods for calculating the amplitudes and characteristic times of the RTS currents produced by traps with known electrical characteristics and locations are described. The noise spectra in junction field effect transistors (JFET's) resulting from traps in the silicon or the oxide are derived as a function of basic device parameters, operating conditions and temperature. Experimental results verifying the predictions of the models are presented     

Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit

In this paper, we present extensive random telegraph signal (RTS) noise characterization in SiGe heterojunction bipolar transistors. RTS noise, observed at the base, originates at the emitter periphery while at the collector side distinct RTS noise is observed at high-injection that originates from the traps in the shallow trench regions. Time constants extracted from RTS during aging tests allow understanding of trap dynamics and new defect formation within the device structure. This paper provides the first demonstration of RTS measurements during accelerated aging tests to study and understand generation of defects under bias stress in SiGe HBTs operating at the limit of their safe-operating area.     

Random Telegraph Signal Noise in Gate-All-Around Si-FinFET With Ultranarrow Body

For the first time, the random telegraph signal (RTS) and its corresponding flicker noise$(1/f)$were investigated in gate-all-around p-type Si-FinFETs. For a device with gate width of$sim$100 nm (fin height) and length of$sim$200 nm, the typical RTS capture/emission time constants were$sim$0.1–1 ms. Very large RTS amplitudes ($Delta I_d/I_d$up to 25%) were observed, which is an effect attributable to the extreme device scaling and/or interface quality of FinFETs. The estimated scattering coefficients$(alpha sim hbox10^-12 - hbox10^-13)$are found to be higher than typical values obtained from MOSFETs. These findings demonstrate the relevance of RTS for FinFET operation.     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

Impact of Top-Surface Tunnel-Oxide Nitridation on Flash Memory Performance and Reliability

Two approaches to top-surface nitridation of tunnel oxide, i.e., rapid thermal nitridation using $hbox{NH}_{3}$ anneal and decoupled plasma nitridation, are compared. Floating-gate MOS capacitors with source/drain were used to evaluate Flash memory performance and reliability. Tunnel-oxide $hbox{NH}_{3}$ anneal degrades postcycling retention performance compared to plasma nitridation for the same equivalent oxide thickness reduction. The poorer performance of $hbox{NH}_{3}$ anneal is related to higher N incorporation into $hbox{SiO}_{2}$ bulk rather than top surface. Postcycling memory erase-level shift and memory window (MW) closure is lower for plasma nitridation compared to $hbox{NH}_{3}$ anneal. A new integration scheme using plasma nitridation followed by NO anneal produces the lowest MW closure with cycling.      

Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories

This paper presents a comprehensive investigation of random telegraph noise (RTN) in deca–nanometer Flash memories, considering both the nor and the nand architecture. The statistical distribution of the threshold voltage instability is analyzed in detail, evidencing that the slope of its exponential tails is the critical parameter determining the scaling trend for RTN. By means of 3-D TCAD simulations, the slope is shown to be the result of cell geometry, atomistic substrate doping, and random placement of traps over the cell active area. Finally, the slope dependence on cell geometry (width, length, and oxide thickness), doping, and bias conditions is summarized in a powerful formula that is able to predict the RTN instabilities in deca–nanometer Flash memories.      

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.     

Hot-carrier stress effects on the amplitude of Random Telegraph Signals in small area Si p-MOSFETS

This paper studies the effect of avalanche hot-carrier (HC) stress on the amplitude of pre-existing Random Telegraph Signals (RTSs) in small area Si p-MOSFETs. It is shown that the RTS amplitude of a particular oxide trap increases after HC stress, both in linear operation and in saturation. From this, it is concluded that the effect of such a trap on the carrier transport in a small area MOSFET is also determined by the charges present at the interface and in the oxide. The impact of the observations on the RTS based modeling of flicker noise in MOSFETs will be briefly addressed.     

Read disturb in flash memories: reliability case

It is known that program/erase cycling of Flash memories induces a degradation of the tunnel oxide insulating property usually referred to as Stress-Induced Leakage Current (SILC). An issue related to SILC is the read disturb, affecting cells in an addressed word-line, which can cause electron injection through tunnel oxide in the floating gate of erased cells during read operation. Read disturb can also be present in Flash memory with a weak tunnel oxide quality: aim of this paper is to discuss in detail the effect of this read disturb phenomena. Cell Failure Density (CDF) extrapolation from experimental data using statistical method is able to estimate defect probability and application’s failure rate for both SILC and weak tunnel oxide quality cases.     

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equations are derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated programming and erasing characteristics and transconductance and subthreshold slope $(g_{m}/SS)$ behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC $I$– $V$, as well as programming and erasing characteristics, and these must be taken into account in memory circuit design.