An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented.This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel.Experimental results show the measured pinch-off voltage is consistent with theoretical prediction.This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sen...     

A log-polar image sensor fabricated in a standard 1.2-μm ASICCMOS process

A CMOS log-polar or foveated image sensor for use in mobile robotic and machine vision applications has been designed, fabricated, and tested. The sensor benefits from a high degree of integration, minimal power consumption, and ease of manufacture due to the use of a standard 1.2 μm ASIC CMOS process. The sensor is composed of two distinct CMOS imager arrays which together solve the problem of obtaining good image resolution over a wide field of view. With resolution sensing is accomplished with a 40×40 array of individual pixels each measuring 9.6 μm on a side. A wide field of view is provided by an array of 64×16 pixels arranged on a log-polar grid. The maximum measured dynamic range for the fabricated log-polar array is 46 dB, while the lowest observed fixed-pattern noise is 0.5% of saturation. Combined power consumption of both arrays is under 2 mW when operating from a single 5-V supply at a frame rate of 30 frames/s     

一种获得四管CMOS图像传感器像素夹断电压的方法

提出了一种测试四管CMOS图像传感器像素夹断电压的方法。该方法是基于像素中势阱结构的变化能够对图像信号散粒噪声产生影响的假设。实验结果测得的夹断电压与理论预测相一致。该技术提供的实验方法不仅能够帮助设计四管CMOS图像传感器光电二极管的结构,而且也能优化像素生产工艺。     

CMOS foveated image sensor: signal scaling and small geometryeffects

A new foveated (log-polar) image sensor using standard CMOS technology has been designed and fabricated. The pixel distribution follows the log polar transform having more resolution in the center than in the periphery. For the fovea or central part, a different but also polar distribution has been adopted to fit the inner pixels. The particular problem of foveated image sensors is the signal scaling; pixels at different positions are different sizes and therefore different signal responses to the same illumination level. The difference among pixel responses is not only due to the differences among sensitive areas, but also to the differences among transistor channel sizes that, for submicron technologies, become a nonlinear problem. Some solutions for the signal scaling, small geometry effects (especially narrow-channel effects), and foveated structure, have been analyzed and successfully adopted for the presented sensor. The election of the CMOS process, instead of the CCD, is also discussed and analyzed     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

Wide-Angle Foveation for All-Purpose Use

This paper proposes a model of a wide-angle space-variant image that provides a guide for designing a fovea sensor. First, an advanced wide-angle foveated (AdWAF) model is formulated, taking all-purpose use into account. This proposed model uses both Cartesian (linear) coordinates and logarithmic coordinates in both planar projection and spherical projection. Thus, this model divides its wide-angle field of view into four areas, such that it can represent an image by various types of lenses, flexibly. The first simulation compares with other lens models, in terms of image height and resolution. The result shows that the AdWAF model can reduce image data by 13.5%, compared to a log-polar lens model, both having the same resolution in the central field of view. The AdWAF image is remapped from an actual input image by the prototype fovea lens, a wide-angle foveated (WAF) lens, using the proposed model. The second simulation compares with other foveation models used for the existing log-polar chip and vision system. The third simulation estimates a scale-invariant property by comparing with the existing fovea lens and the log-polar lens. The AdWAF model gives its planar logarithmic part a complete scale-invariant property, while the fovea lens has 7.6% error at most in its spherical logarithmic part. The fourth simulation computes optical flow in order to examine the unidirectional property when the fovea sensor by the AdWAF model moves, compared to the pinhole camera. The result obtained by using a concept of a virtual cylindrical screen indicates that the proposed model has advantages in terms of computation and application of the optical flow when the fovea sensor moves forward.     

用于百万像素级CMOS图像传感器的10位50MS/s流水线ADC设计

高速高精度ADC是CMOS图像传感器中的重要部分。随着工艺的进步,低功耗设计已经吸引了很多人的注意。为了在没有降低表现的情况下控制功耗,在本设计采用相同结构放大器共用相同的偏置电路技术,并且采用了共源共栅补偿技术来降低功耗。噪声和不匹配也是流水线ADC中重要的误差源,因此采用了Matlab对这两者进行了仔细的计算和系统仿真。在本文中,提出了一个10位50MS/s的 流水线ADC核心。这个设计可以用于大像素规模的CMOS图像传感器。本设计在表现和功耗上取得了很好的平衡。     

Test chip for the development and evaluation of sensors for measuring stress in metal interconnects

The development of a new test chip is presented, containing structures for the direct measurement of stress in metallic interconnect layers associated with silicon integrated circuit technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip design has been used to fabricate working structures allowing the study of stresses in aluminum layers before and after sample sintering. The results are presented together with the design, fabrication, and measurement considerations that have arisen during the research. The problems experienced in removing the sacrificial layer material, necessary to release the structures, are discussed along with potential solutions. The sensor structure is suitable for fabrication within a CMOS facility and its inherent scalability makes it potentially suitable for in-line testing of state-of-the-art processes.     

基于4T像素结构的CMOS图像传感器设计

传统的CMOS图像传感器采用3T像素结构,但由于自身结构的关系,整体性能难以满足较高的要求,4T像素结构应运而生,它比3T像素有更小的噪声,更好的性能;同时要求控制部分更加复杂。文中介绍了基于一种4T像素结构的图像传感器的设计。     

A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition

An alternative image decomposition method that exploits prediction via nearby pixels has been integrated on the CMOS image sensor focal plane. The proposed focal plane decomposition is compared to the 2-D discrete wavelet transform (DWT) decomposition commonly used in state of the art compression schemes such as SPIHT and JPEG2000. The method achieves comparable compression performance with much lower computational complexity and allows image compression to be implemented directly on the sensor focal plane in a completely pixel parallel structure. A CMOS prototype chip has been fabricated and tested. The test results validate the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate with much lower data readout volume. The features of the proposed decomposition scheme also benefit real-time, low rate and low power applications.      

CMOS工艺兼容多晶硅压力敏感膜的设计与加工

在MEMS表面加工工艺中 ,多晶硅薄膜是微结构的重要组成部分。本文考虑加工工艺中残余应力的影响和多晶硅材料的强度范围 ,建立多晶硅膜的大变形模型 ,设计可用于压力传感器应用的多晶硅薄膜几何尺寸。采用有限元方法对多晶硅薄膜进行力学分析和设计验证 ,提出了CMOS工艺兼容的多晶硅压力敏感膜的加工方法 ,并且根据所设计的工艺进行了电容式压力传感器微结构的加工 ,加工结果说明了多晶硅薄膜设计的合理性和CMOS兼容工艺的可行性     

基于FPGA的CMOS传感器高速视频采集系统

依据图像采集和传输的方式和方法的不同,提出了一种以CMOS数字图像传感器作为相机光电转换器件的数据采集方法.设计了一种利用FPGA作为核心控制芯片、USB为传输接口、CMOSOV5620为图像采集芯片的高速视频采集系统.介绍了系统的总体设计结构,给出了各个模块的具体硬件设计方法和软件流程,得出了可行性结论.     

Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

With the scaling development of the minimum lithographic size, the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule. When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD imagepixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction, which results in pixel crosstalk. The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling. Some suppressed crosstalk methods have been reviewed. The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.     

Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor

An optimum design theory to clarify a possible limit of achieving both high conversion gain (CG) and full well capacity (FWC) at the same time in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) in a pixel is discussed. The possible limit of both high CG and high FWC is theoretically derived from a signal-to-noise-ratio (SNR) formula at a switching point from a low light signal (S1) to a bright one (S2). Based on this theory, a 1/4-in VGA-format 5.6-mum-pixel-pitch CMOS image sensor has been fabricated through a 0.18-mum 2P3M CMOS technology. A high-quality wide-dynamic-range image sensing has been demonstrated with no significant visible noise, achieving over 32 dB of SNR for an 18% gray card.     

Random addressable 2048×2048 active pixel image sensor

In this paper, we discuss the design, design issues, fabrication, and performance of a 2048×2048 active pixel image sensor in a 0.5-μm standard CMOS process. Each pixel, 7.5×7.5 μm² , consists of three transistors and a photo diode, resulting in a 12-million transistor chip with a die size of 16.3×16.5 mm. The pixel has a nonintegrating direct readout architecture, with a logarithmic light-to-voltage conversion. This allows the array to be fully random accessible, both in space and time. The sensor has eight analog outputs, each with a pixel rate of 4.5 MHz, which implies a maximum frame rate of eight full frames per second. Sub-sampling or windowing makes higher frame rates possible. The yield of the sensor is high if one accepts a small number of bad pixels     

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01％ of the whole chip power consumption.     

CMOS图像传感器的研究新进展

随着超大规模集成技术的发展,CMOS图像传感器显示出了强劲的发展趋势.简要介绍了CMOS图像传感器的发展历程,在分析CCD和CMOS图像传感器工作原理的基础上,对比了CMOS图像传感器与CCD的特点.重点描述了国外CMOS图像传感器的最新商业化产品状况,同时给出了一些产品的性能参数,最后展望了CMOS图像传感器的未来发展趋势.     

Real-time restoration of images degraded by uniform motion blur infoveal active vision systems

Foveated, log-polar, or space-variant image architectures provide a high resolution and wide field workspace, while providing a small pixel computation load. These characteristics are ideal for mobile robotic and active vision applications, but have been little used due to the general lack of image processing tools that are applicable to the log-polar coordinate system. Recently, we have described a generalization of the Fourier transform (the fast exponential chirp transform), which allows frame-rate computation of full-field two-dimensional (2-D) frequency transforms directly in log-polar coordinates. In the present work, we show that is possible to achieve full-frame image de-blur at frame rate on a standard "PC" platform, using these methods, we illustrate this idea with a Wiener filter based restoration technique. The main contribution of this note is the implementation of (space-variant) image de-blur directly in log-polar coordinates, using the exponential chirp transform. The results show reasonable quality of de-blur, and suggest that these methods are relevant to applications in mobile image processing platforms in which real-time motion deblur is important, and for which it is not desirable to use extensive or custom fabricated hardware.     

Simple and quick turnaround time fabrication process for deepsubmicrometer CMOS generation

Process simplification and turnaround time reduction for deep submicrometer CMOS fabrication are discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation processes are extracted as items for process simplification. A combination of shallow trench isolation with retrograde well structure and single mask step well/gate doping technique is proposed for deep submicrometer CMOS fabrication. This simplified CMOS process can achieve a reduction of five mask steps and eliminates both well drive-in annealing and field oxidation without performance deterioration. As a result, a 10% process step reduction and a 20% manufacturing turnaround time reduction have been realized in comparison to the standard 1Poly/1Metal CMOS process with LOCOS isolation     

A 200-$mu$V/e$^{-}$ CMOS Image Sensor With 100-ke$^{-}$ Full Well Capacity

A high-sensitivity CMOS image sensor keeping a high full-well capacity has been developed by introducing a new pixel having a small floating diffusion (FD) capacitance connected to a lateral overflow integration capacitor (LOFIC) through a MOS switch. The conceptual advantage of the small FD approach over conventional column amplifier approaches is compared and demonstrated. To ensure both the high sensitivity and the high full-well capacity, the low-light and the bright-light signals (S1 and S2) are output and reproduced without a visible SNR degradation at the S1/S2 switching point. As the most critical problem, the increase of the conversion gain variation in this approach is suppressed by applying a self-aligned offset structure to the small FD. A 1/4-in VGA format CMOS image sensor fabricated through 0.18-mum 2P3M process achieves 2.2-e^- rms noise floor with 200-muV/e^- conversion gain and 100-ke^- full-well capacity.