用于模拟电路行为级建模的自动压扩子波方法

提出了一种新的自动压扩方法,适用于基于子波配置方法的模拟电路行为级建模.该压扩方法采用的压扩函数根据模块输入-输出函数的奇异性自动生成,因而这一方法具有通用性,可应用于任意输入-输出函数的电路模块的建模.与已有的建模方法相比,该方法能有效地降低模拟误差并减少使用基函数的个数.     

非线性自动压扩的开关电流电路行为级建模方法

提出了一种新的基于非线性压扩函数自动构造的开关电流电路行为级建模方法,从而简化电路的建模和仿真.与原有的建模方法相比,该方法不仅可以对模型的误差分布进行有效地调控,而且能够降低模型的误差.为了验证本文所提出的行为级建模方法,对几种开关电流电路进行了建模和模拟试验.     

非线性自动压扩的开关电流电路行为级建模方法

提出了一种新的基于非线性压扩函数自动构造的开关电流电路行为级建模方法,从而简化电路的建模和仿真.与原有的建模方法相比,该方法不仅可以对模型的误差分布进行有效地调控,而且能够降低模型的误差.为了验证本文所提出的行为级建模方法,对几种开关电流电路进行了建模和模拟试验.     

一种输入级模块复用的In-Zn-O薄膜晶体管行集成驱动电路

提出了一种新型的基于In-Zn-O薄膜晶体管(IZO TFT)的行集成驱动电路。该电路采用了输入级模块复用的驱动方法,即一级输入级驱动多级输出级,因此可以显著地减少输入级模块TFT的数量,缩减电路的面积,满足高分辨率显示屏设计,同时也可以迎合显示屏窄边框的审美需求。电路的输入级模块工作时间是输出级模块的n倍(n是一级输入级模块驱动输出级模块的级数),因此输入级尺寸可以做得更小。另外,该电路的驱动时钟频率是传统结构中一级输入级模块驱动一级输出级模块时钟频率的1/n,有效地降低了电路的动态耦合功耗。我们制作了20级的行集成驱动电路,一级输入级模块驱动两级输出级模块,该电路的尺寸为宽730μm,高为164μm,满足窄边框的要求。从实验测结果表明,该电路很好地满足300PPI的AMLCD或AMOLED显示屏的需求。     

一种适用于开关电源的内部供电电路设计

本文提出了一种适用于开关电源的内部供电电路。该电路采用齐纳二极管的稳压原理,将开关电源的高输入电压稳压输出5V,供模拟模块和数字模块使用,简化了以往采用基准和低压差线性稳压器(LDO,Low Dropout Regulator)供电的设计方法。本电路基于0.35 um BCD工艺,对所设计电路进行了仿真验证。仿真结果表明,该电路在-40℃~125℃应用环境温度范围内都能够实现高精度的输出电压,具有较强的稳定性。     

一种低抖动、宽调节范围的带宽自适应CMOS锁相环

提出了一种低抖动、宽调节范围的带宽自适应CMOS锁相环.由于环路带宽可根据输入频率进行自动调节,电路性能可在整个工作频率范围内得到优化.为了进一步提高电路的抖动特性,在电荷泵电路中采用匹配技术,并在压控振荡器中应用电压-电压转换电路以减小压控振荡器的增益.芯片采用SMIC 0.35μm CMOS工艺加工.测试结果表明该锁相环电路可在200MHz～1.1GHz的输出频率范围内保持良好的抖动性能.     

输电线路架空地线取电系统电源变换模块仿真设计

本文为输电线路架空地线取电系统设计出配套的电源变换模块,并对模块电路进行了仿真分析。该电源变换模块可以实现9~100V交流输入到12V直流输出的转换。通过设计整流电路、搭建电路模型、分析电路的输入输出特性,从而得到相对稳定的直流电压源。通过设计电压变换电路将整流电路输出的直流电压进行转换,得到系统所需的12V直流电压,文中优化了电路控制信号脉冲占空比,得到了不同输入电压情况下的最优脉冲占空比,拟合出最优占空比随输入电压变化曲线。     

一种低抖动、宽调节范围的带宽自适应CMOS锁相环

提出了一种低抖动、宽调节范围的带宽自适应CMOS锁相环.由于环路带宽可根据输入频率进行自动调节,电路性能可在整个工作频率范围内得到优化.为了进一步提高电路的抖动特性,在电荷泵电路中采用匹配技术,并在压控振荡器中应用电压-电压转换电路以减小压控振荡器的增益.芯片采用SMIC 0.35μm CMOS工艺加工.测试结果表明该锁相环电路可在200MHz～1.1GHz的输出频率范围内保持良好的抖动性能.     

一个用于电路设计的实验性专家系统“模块”

建立了一个用于模拟电路设计的称为“模块”的实验性专家系统,目的在借此研究实现高水平电路专家系统的途径及方法。“模块”系统只需根据给定的对电路的输出及输入信号的要求,就能自动而快速地完成电路的方框设计,而这些工作通常是需要由电路设计者来完成的。     

基于RT8482的大功率LED驱动电路设计

根据发光二极管的V-I特性,设计了一款基于RT8482芯片的升压恒流大功率LED驱动电路,其输出电压自适应。该电路主要包括输入电源反接保护单元、LED升压恒流驱动单元、PWM数字调光与变阻模拟调光单元、扩流输出单元等,电路同时还具有过压保护、过流保护等功能。测试结果及实际使用表明：该电路在12V输入电压下驱动84w大功率白色LED灯珠阵列时输出电流恒定,其效率可达89．16％,且亮度调节范围宽、精度高,适用于通用与景观照明、汽车照明、室内装饰及电子设备背光等大功率LED照明应用领域。     

Circuit models for three-dimensional geometries includingdielectrics

The partial element equivalent circuit (PEEC) approach has proved useful for modeling many different electromagnetic problems. The technique can be viewed as an approach for the electrical circuit modeling for arbitrary 3-D geometries. Recently, the authors extended the method to include retardation with the rPEEC models. So far the dielectrics have been taken into account only in an approximate way. In this work, they generalize the technique to include arbitrary homogeneous dielectric regions. The new circuit models are applied in the frequency as well as the time domain. The time solution allows the modeling of VLSI systems which involve interconnects as well as nonlinear transistor circuits     

A New Training Approach for Robust Recurrent Neural-Network Modeling of Nonlinear Circuits

A new approach for developing recurrent neural-network models of nonlinear circuits is presented, overcoming the conventional limitations where training information depends on the shapes of circuit waveforms and/or circuit terminations. Using only a finite set of waveforms for model training, our technique enables the trained model to respond accurately to test waveforms of unknown shapes. To relate information of training waveforms with that of test waveforms, we exploit an internal space of a recurrent neural network, called the internal input-neuron space. We formulate a new circuit block combining a generic load and a generic excitation to terminate the circuit. By sweeping the coefficients of the proposed circuit block, we obtain a rich combination of training waveforms to cover the region of interest in the internal input-neuron space effectively. We also present a new method to reduce the amount of training data while maintaining the necessary modeling information. The proposed method is demonstrated through examples of recurrent neural-network modeling of high-speed drivers and an RF amplifier. It is confirmed that, for different terminations and test waveforms, the model trained with the proposed technique has better accuracy and robustness than that using the existing training methods.      

Equivalent circuit representation of open guided-wave structures

A modular equivalent circuit representation for modeling and analyzing open guided-wave structures, which takes into account both the guided and the continuous spectra, is discussed. In the development of the technique approximations that are valid for integrated optics in III-V compound semiconductors are utilized. The validity of these approximately was assessed on the basis of both physical arguments and numerical simulations. Results obtained with the present method are compared with the results of other methods of analysis for rectangular fiber and rib guides with sloped rib sides. The present method gives accurate results with limited computational effort and can analyze a wide variety of integrated optical components ranging from single waveguides of arbitrary cross-sectional profile to multiple coupled guides of arbitrary widths and spacings     

结合电路结构基于分块的诊断方法

基于模型的诊断问题在人工智能领域内一直备受关注,将诊断问题转换成SAT （Satisfiable）问题成为解决基于模型诊断问题的一个重要方法.基于目前高效诊断方法LLBRS-Tree （Last-Level Based on Reverse Search-Tree）的研究,本文提出电路分块诊断方法ACDIAG （Abstract Circuit Diagnosis）方法,对电路进行分块来缩减电路规模,利用LLBRS-Tree方法对分块后抽象电路求得极小块诊断解;提出诊断解拓展方法,结合分块后电路结构特征对每个极小块诊断解进行直接扩展得到极小诊断解,避免对抽象电路还原后才能得到所有解的问题.     

A New Approach to Dyadic Green''s Function in Spectral Domain

A new method is proposed to derive the dyadic Green's function for stratified dielectric layers from the wave equation in spectral domain. The result is a clear equivalent circuit of the whole structure which combines the TE and TM modes by hybrid block matrices. It is simple to apply and evaluate. The relation to the conventional immittance approach is shown by means of a similarity transform which diagonalizes the submatrices. The simplicity of the method is demonstrated in the application to the well-known example of a single microstrip patch on a grounded dielectric layer as well as structures with multiple layers and metallizations in arbitrary interfaces     

基于verilog-A数控LC振荡器系统的行为级建模

在全数字锁相环中数控振荡器和由∑△调制器所构成的系统是一个规模很大的电路,采用传统的电路级描述难以在现有的EDA工具中仿真.为此提出了一种基于Verilog-A语言的行为级建模方法来对系统进行仿真.详细介绍了数控振荡器系统中各模块的建模方法,并给出了各模块建模的关键代码.仿真结果表明对数控振荡器的行为模型不仅能提高仿真效率还能很好模拟实际系统.该行为模型具有较好的实用性,所得结果可用于指导具体电路的设计.     

Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods

This paper introduces an efficient and passive discrete modeling technique for estimating signal propagation delays through on-chip long interconnects that are represented as distributed RLC transmission lines. The proposed delay model is based on a less frequently used numerical approximation technique, called the differential quadrature method (DQM). The DQM can compute the partial derivative of a function at any arbitrary point located within a prespecified closed domain of the function by quickly estimating the weighted linear sum of values of the function at a relatively small set of well-chosen grid points within the domain. By using the fifth-order DQM, a new approximation framework is constructed in this paper for discretizing the distributed RLC interconnect and thereafter modeling its delay. Due to high efficiency of DQM approximation, the proposed framework requires only few grid points to achieve good accuracy. The presented equivalent-circuit model appears like the ones derived by the finite difference (FD) method. However, it has higher accuracy and less internal nodes than generated by the FD-based modeling. The fifth-order DQM modeling technique is shown to preserve passivity. It has linear forms that are compatible with the passive order-reduction algorithm for linear network. Numerical experiments show that the proposed modeling approach leads to high accuracy as well as high efficiency.     

Calculation of the original of response of multiinput nonlinear wireless devices using the Volterra series

A computing method has been proposed for calculating the original of response under the action of complex signals of multiinput nonlinear devices by using the tool of Volterra functional series. This method is based on the technique of determining Volterra kernels by differentiation of the system of harmonic balance equations and the procedure of transition to a single variable in the domain of transforms. A response in the time domain can be obtained by using the one-dimensional Laplace transform in the form of function of circuit parameters and input actions where the characteristics of nonlinear elements are approximated by an arbitrary analytic function. This study includes an example of computing the original of response of a nonlinear circuit with two inputs.     

Circuit Modeling of Interdigitated Capacitors Fabricated by High‐K LTCC Sheets

The circuit modeling of interdigitated capacitors fabricated by high‐k low‐temperature co‐fired ceramic (LTCC) sheets was investigated. The s‐parameters of each test structure were measured from 50 MHz to 10 GHz, and the modeling was performed using these measured s‐parameters up to the first resonant frequency. Each test structure was divided into appropriate building blocks. The equivalent circuit of each building block was composed based on the partial element equivalent circuit (PEEC) method. Modeling was executed to optimize the parameters in the equivalent circuit of each building block. The validity of the extracted parameters was verified by the predictive modeling for the test structures with different geometry. After that, Monte Carlo analysis and sensitivity analysis were performed based on the extracted parameters. The modeling methodology can allow a device designer to improve the yield and to save time and cost for the design and manufacturing of devices.     

Efficient Look-Up-Table-Based Modeling for Robust Design of Σ∆ ADCs

The sigma-delta (SigmaDelta) analog-digital converter (ADC) has been widely used in data conversion applications due to its good performance. However, oversampling and complex circuit behaviors render the transistor-level analysis of these designs prohibitively time consuming. The inefficiency of the standard simulation approach also rules out the possibility of analyzing the impacts of a multitude of environmental and process variations critical in modern VLSI technologies. We present a look-up table (LUT)-based modeling technique to facilitate much more efficient performance analysis of SigmaDelta ADCs. Various transistor-level circuit nonidealities are systematically characterized at the building block level and the whole system is simulated much more efficiently using these building block models. Our approach can provide up to four orders of magnitude runtime speedup over SPICE-like simulators, hence significantly shortening the CPU time required for evaluating system performances such as signal-to-noise-and-distortion ratio. The proposed modeling technique is further extended to enable scalable performance variation analysis of complex SigmaDelta ADC designs. Such modeling approach allows us to perform trade-off analysis of various topologies considering not only nominal performances but also their variabilities. Equally important, with our efficient parametric modeling technique, we are able to feasibly extract simulation-based statistical performance correlation models allowing low-cost alternate linearity test of ADC designs.