A methodology to extract the channel current of permeable gate oxide MOSFETs

A methodology to extract the channel current of MOS transistors in the presence of high gate leakage current is presented. The methodology is based on the partitioning of the gate current among the source and drain terminals and it is well suited for devices featuring ultrathin gate oxide and long channels, as those typically employed for mobility measurements. The proposed procedure is compared with the existing method based on a 50%-50% source/drain partition of the gate current, and the dependence of the extraction error associated with these two methods on channel length and bias conditions is studied in detail. It is found that the extraction error is weakly dependent on gate-source and drain-source voltages.     

A theoretical model for the current-voltage characteristics of afloating-gate EEPROM cell

A model for current-voltage characteristics of an EEPROM cell has been developed and used in the simulation of an EEPROM test structure. It provides an explanation for the observed strong drain-induced barrier lowering effect and the role of trapped charge in the floating gate. In this model, the surface potential is related to the terminal voltages through an equivalent electrical circuit. Charge sheet and depletion approximation are used to describe the charge distribution in the semiconductor. Gradual approximation is assumed in deriving the drain current equation. A simplified drain current equation under a strong inversion condition is derived. An expression defining the extrapolated threshold voltage is obtained. It is useful in parameter extraction. A new method for extracting the drain coupling ratio and the channel coupling ratio is proposed. Finally, it is shown that extrapolated threshold voltage is a convenient quantity for classifying the threshold voltage of an EEPROM cell     

Model for the channel-implanted enhancement-mode IGFET

A simple dc four-terminal "channel-implanted model" is developed for the enhancement-mode IGFET. The model accurately predicts the dependence of transistor threshold voltage and current gain on substrate bias. Modeled and measured threshold voltages are shown to agree to within 25 mV across a 15-V range of VSB. Modeled and measured transistor currents agree to within 5 percent across a 10-V range of VSBfor medium- to long-channel length transistors (L_{drawn} ge 2.5µm). The channel impurity profile is approximated as a constant effective impurity concentration NAEextending from the semiconductor surface through the implanted region to an effective implant depth XDE("box" profile approximation). At depths greater than XDE, the bulk substrate impurity concentration is approximated as a constant, NA. The model is composed of two threshold voltage equations, three drain current equations, two saturation voltage equations, and two boundary equations. All first-order model equations and all of their first derivatives are continuous at all boundaries. The model's continuity and its accuracy make it useful for circuit simulation. Extrapolation of channel concentration profile parameters NAE, XDE, and NAfrom measured threshold voltages yields information on implant profile and on field-implant impurity encroachment into the transistor channel.     

Gated-four-probe a-Si:H TFT structure: a new technique to measurethe intrinsic performance of a-Si:H TFT

In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances     

高温CMOS数字集成电路直流传输特性的分析

分析了高温CMOS倒相器和门电路的直流传输特性,建立了相应的解析模型。根据分析,高温MOSFET阈值电压和载流子迁移率的降低,以及MOSFET漏端pn结泄漏电流的增加引起了CMOS倒相器和门电路直流传输特性劣化。在MOSFET漏端pn结泄漏电流的影响下,高温CMOS倒相器和门电路的输出高电平下降,低电平上升,导致了电路的功能失效。给出的理论模型和实验结果一致。     

Effect of operating conditions on reverse gate current of junction f.e.t.s

With some types of nchannel junction f.e.t.s the measurement of gate leakage current under operating conditions (with a current flowing in the channel) has shown a very much higher value than would be expected from the maker's specification of IGSS. The excess gate current which flows at higher channel voltage is proportional to the drain current and has a small negative temperature coefficient.     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

Hysteresis behavior in 85-nm channel length vertical n-MOSFETsgrown by MBE

Vertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages V_DS>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode     

GaN/AlGaN p-channel inverted heterostructure JFET

A novel GaN/AlGaN p-channel inverted heterostructure junction field-effect transistor (HJFET) with a n/sup +/-type gate is proposed and demonstrated. A new superlattice aided strain compensation techniques was used for fabricating high quality GaN/AlGaN p-n junction. The p-channel HJFET gate leakage current was below 10 nA, and the threshold voltage was 8 V, which is close to that of typical n-channel HFETs. This new HJFET device opens up a way for fabricating nitride based complimentary integrated circuits.     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

MOSFET's in the 0°K approximation: Static characteristics of MOSFET's in the 0°K approximation

The static electrical characteristics below current saturation of MOSFET's with degenerate source and drain regions are calculated for operation at 0°K. The expression for current takes the same form as at room temperature although the flat-band voltage and the voltage across the depletion region at threshold are altered slightly. Potential hills occur in the channel if the gate does not overlap source and drain or if the oxide thickness is increased in the overlap regions. Although these barriers do not affect operation appreciably at room temperature, at 0°K a finite drain voltage (source-drain threshold voltage) is required to initiate conduction. This threshold voltage is included in the theory and the theory is compared with experimental results on p-channel enhancement mode MOSFET's at 4·2°K using hole mobility in the channel as a matching parameter. The channel hole mobility (assumed constant along the channel) is found to be relatively independent of gate voltage but to increase with increasing (negative) drain voltage. Values ranging between 500 and 1000 cm²/V-sec are deduced for drain voltages ranging from ?1·2 V to ?7 V. This compares to channel hole mobility values of 200–300 cm²/V-sec at room temperature. It is found that the channel width is on the order of 30–50 Å—appreciably less than that at room temperature.     

Determination of AlGaAs/GaAs HEMT parasitic resistances

An improved technique has been developed to measure source and drain parasitic resistances of AlGaAs/GaAs HEMTs. Similar to the measurement technique typically used for MESFETs, a positive d.c. gate crowding current is applied. Because of the structure of the HEMT, this gate current must be kept very small in order to prevent significant leakage into the AlGaAs layer, which would result in current paths not present in normal operation of the device. The small d.c. gate current necessary to limit the current in this leakage path did not yield a usable signal-to-noise ratio of the measured gate-source, gate-drain and drain-source voltages needed to calculate the parasitic resistances. To overcome this problem, modulation of the drain current with a low-frequency a.c. signal coupled with lock-in techniques to measure the desired voltages was implemented. The resulting improvement in signal-to-noise ratio has made the gate crowding technique suitable for measuring the parasitic resistances of AlGaAs/GaAs HEMTs.     

Hot-electron currents in very short channel MOSFET's

The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be Te= 9.05 × 10^-3E.     

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (VD), and an inverse dependence on oxide capacitance (εox/tox). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (tox, VD, L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.     

Gate current in self-aligned n-channel and p-channel pseudomorphicheterostructure field-effect transistors

A report is presented on the results of the study of the gate leakage current in n-channel and p-channel self-aligned pseudomorphic HIGFETs. The authors demonstrate that in these devices the gate leakage current is practically independent of the gate length. This means that the gate current primarily flows into the source and drain contacts through small sections of the channel near the contacts. At large gate voltages, the gate current is limited by the band discontinuities at the heterointerface, similar to the gate current in non-self-aligned heterostructure field-effect transistors     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

Subthreshold conduction in MOSFET's

The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.     

Low-level gate current injections in flash memories initiated byminority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low     

Excess gate current in the static induction transistor

In SIT devices an excess gate current flows at high drain-source voltages. This current originates from an impact multiplication of the drain current majority carriers. A simple method is presented for the calculation of this excess current. The method is based on a one dimensional analysis of the potential distribution and the ionization integral. Good agreement between measured and calculated results has been achieved.