一种低压低功耗衬底驱动轨至轨运算放大器设计

介绍了一种基于衬底驱动技术的低电压低功耗运算放大器.输入级采用衬底驱动MOSFET,有效避开阈值电压限制;输出采用改进前馈式AB类输出级,确保了输出级晶体管的电流能够得到精确控制,使输出摆幅达到轨至轨.整个电路采用PTM标准0.18μm CMOS工艺参数进行设计,用Hspice进行仿真.模拟结果显示,测得直流开环增益为62.1 dB,单位增益带宽为2.13 MHz,相位裕度52°,电路在0.8 V低电压下正常运行,电路平均功耗只有65.9μW.     

A readout circuit for an intra-ocular pressure sensor

A readout circuit for a passive telemetric intra-ocular pressure (IOP) sensor is being developed. The intra-ocular sensor consists of a capacitive pressure sensor in parallel with a planar coil. This inductor–capacitor (LC) resonant circuit transduces the pressure into a shift of resonance frequency. A voltage controlled oscillator (VCO) is used to excite the sensor over a large frequency range (20–40 MHz), hereby detecting resonance of the internal sensor, and thus enabling the measurement of the intra-ocular pressure. This low power circuit is extremely compact, making it suitable for long-term ambulant patient monitoring. The circuit allows wireless readout of the smallest pressure transducers. Tests show promising results at mutual coil distances up to 7.5 mm.     

A new discrete circuit for readout of resistive sensor arrays

In this paper, we present a method that simplifies the interconnect complexity of N × M resistive sensor arrays from N × M to N + M. In this method, we propose to use two sets of interconnection lines in row–column fashion with all the sensor elements having one of their ends connected to a row line and other end to a column line. This interconnection overloading results in crosstalk among all the elements. This crosstalk causes the spreading of information over the whole array. The proposed circuit in this method takes care of this effect by minimizing the crosstalk. The circuit makes use of the concept of virtual same potential at the inputs of an operational amplifier in negative feedback to obtain a sufficient isolation among various elements. We theoretically present the suitability of the method for small/moderate sized sensor arrays and experimentally verify the predicted behavior by lock-in-amplifier based measurements on a light dependent resistor (LDR) in a 4 × 4 resistor array. Finally, we present a successful implementation of this method on a 16 × 16 imaging array of LDR.     

一种低功耗的微弱能量收集电路设计

为了实现高效率地收集环境中的各种微弱能量,设计了一种低功耗的微弱能量收集电路。采用LTC3588-1电源管理芯片为核心的电压变换电路、LTC4071充电控制芯片为核心的充电控制电路、TPL5100为核心的定时器电路搭建低功耗微弱能量收集电路,设计的电路能够将收集到的微弱能量转换为电能存储到锂电池或者提供给负载供电。实验结果表明,设计的低功耗微弱能量收集电路实现了微弱能量的收集,能量收集电路自身平均功耗低至182μW,验证了收集微弱能量给无线传感器网络节点供能的可行性,电路因低功耗、低成本等优点,具有应用前景。     

一种低噪声的生物微传感器CMOS读出电路研究

为提高生物微传感器的探测灵敏度,设计了一种低噪声的生物微传感器CMOS读出电路,提出了一种新型的相关双采样(CDS)电路.对读出电路的噪声进行抑制.在0.6μm CMOS工艺下,用Spectre仿真器对该电路进行了模拟,仿真结果表明,采用相关双采样的CMOS读出电路使传感器的输入输出转换具有良好的线性关系.     

一种电流积分型生物传感微阵列信号读出电路

设计了一种用于自组装膜生物传感阵列的高灵敏度信号读出电路,该电路主要包括高灵敏度微阵列生物电流探测单元、积分单元、相关双采样(CDS)单元及输出缓冲单元。电路采用单5 V电源,输入电流为0~50 nA,在0.6μm/level 7 CMOS工艺条件下进行模拟,得到了较为满意的结果。该读出电路与标准CMOS工艺兼容,可实现集成的生物传感阵列。     

脑电检测前置放大器静电保护电路的设计

以CMOS仪表运算放大器作为脑电检测前置放大器是经常选择的技术方案。但是,在使用过程中人体静电所产生的高能电子流会击穿COMS管的绝缘栅并停留在那里,从而使得放大器无法正常工作。采用在输入回路中并接二极管或电容器的方法可以实现静电保护,但由于器件参数的不对称性将极大地降低系统的共模抑制比。为此设计了一个有源储能电路,通过该电路能精密调节等效电容量的大小,在不影响共模抑制比的前提下,提高了放大器的抗静电能力,增强了系统的可靠性。     

一种低功耗同步BUCK芯片的过零检测电路设计

同步BUCK芯片在轻载模式下会产生因电感电流倒灌而产生的额外功耗。针对这一问题,设计了一款过零检测电路。该电路采用两个不同电压门限采集技术,并对门限进行温度补偿,有效限制了电感电流的倒灌;同时设计了边沿隐匿电路,避免电路切换时引起的误触发。该过零检测电路基于0.25μm BCD工艺设计,利用HSPICE仿真验证。当系统温度在-40℃~120℃变化时,负阈值电压容差仅为0.2 m V,实现了高精度的过零检测,且静态功耗极低。     

低温红外面阵读出电路中的高性能缓冲器设计

使用chrt 0.35μm 3.3V CMOS工艺设计了用于制冷型红外面阵读出电路的高性能输出缓冲器,该缓冲器能在红外读出电路5M/s的读出速度下驱动约25pF的负载电容,在输出幅度为2V的条件下,建立时间为40ns,平均功耗为3.94mA。给出了修改chrt 0.35μm后的模型参数的仿真结果与最后的测试结果,基本满足红外读出电路的设计要求。     

A new hybrid fabrication process for a high sensitivity MEMS microphone

A novel multi-layer stacking capacitive type microphone is designed in this study based on theoretical analysis and numerical simulations, while fabricated via two standard stable silicon-based MEMS processes—PolyMUMPs and SOIMUMPs. The adoption of two standardized processes helps greatly to increase yield rate. The sensitivity of the microphone is first determined by an analytical model based on an equivalent circuit, which is followed by finite element (FEM) analyses on the capacitance value, static pull-in voltage and dynamic characteristics. Based on the developed analytical model, varied dimensions of the microphone are optimized and then the performance is validated by analytical simulations. In the next step, micro-fabrication of the microphone is accomplished using two standard processes, PolyMUMPs and SOIMUMPs provided by MEMSCAP. Experiments are conducted to acquire the information of pull-in voltage for safe operation and frequency response in sensitivity for performance evaluation. In the static case, experimental results show a good agreement with the analytical results with 90 Mpa residual stress assumed. As for dynamic validation, the frequency response is measured in an anechoic room adopting the exciting frequency as the audible range from 100–10 kHz. The measured sensitivity is as around 0.78 and 1.7 mV/Pa from 100 to 10 kHz, under the biases of 2 and 4.5 V, respectively. Within the audible frequency range, the proposed device maintains the loss as less as 2.7 dB (ref. to V/Pa), under 3 dB—the commonly acceptable drop within audible frequency range.     

The design of a low-noise preamplifier for MRI

In this paper, a low-noise preamplifier for MRI is designed and studied. A noise matching network consisting of three elements is presented. To the single-stage AsGa-FET preamplifier working at 128 MHz, the measured gain through network analyzer (HP8712C) and noise figure through noise figure analyzer (8970B) are 25 and 0.43 dB, respectively.     

A low-noise fully-differential CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS preamplifier for extracellular neural recording is presented in this paper.The capacitive-coupled and capacitive-feedback topology is adopted.We describe the main noise sources of the proposed preamplifier and discuss the methods for achieving the lowest input-referred noise.The preamplifier has a midband gain of 43 dB and a DC gain of 0.The-3 dB upper cut-off frequency of the preamplifier is 6.8 kHz.The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands.It has an input-referred noise of 3.36 μVrms integrated from 1 Hz to 6.8 kHz for recording the local field potentials(LFPs)and the mixed neural spikes with a power dissipation of 24.75 μW from 3.3 V supply.When the passband is configured as 100 Hz-6.8 kHz for only recording spikes,the noise is measured to be 3.01 μVrms.The 0.115 mm2 prototype chip is designed and fabricated in 0.35-μm N-well CMOS(complementary metal oxide semiconductor)2P4M process.     

Design, fabrication, and characterization of a submicroelectromechanical resonator with monolithically integrated CMOS readout circuit

In this paper, we report on the main aspects of the design, fabrication, and performance of a microelectromechanical system constituted by a mechanical submicrometer scale resonator (cantilever) and the readout circuitry used for monitoring its oscillation through the detection of the capacitive current. The CMOS circuitry is monolithically integrated with the mechanical resonator by a technology that allows the combination of standard CMOS processes and novel nanofabrication methods. The integrated system constitutes an example of a submicroelectromechanical system to be used as a cantilever-based mass sensor with both a high sensitivity and a high spatial resolution (on the order of 10/sup -18/ g and 300 nm, respectively). Experimental results on the electrical characterization of the resonance curve of the cantilever through the integrated CMOS readout circuit are shown.     

低功耗便携式心电仪的设计

介绍了一种低功耗便携式心电仪的设计与实现.采用MSP430F169作为核心控制器,配有心电信号采集调理电路、液晶显示模块和数据存储模块等.该心电仪能够对心电进行实时采集处理、显示,而且可以将存储在SD卡内的数据通过USB接口在上位机上进行显示、分析,功耗低、方便携带,有较强的通用性.     

A circuit representation technique for automated circuit design

We present a method of automatically generating circuit designs using evolutionary search and a set of circuit constructing primitives arranged in a linear sequence. This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to he evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation     

Design and implementation of readout circuit on glass substrate with digital correction for touch‐panel applications

Abstract— A readout circuit on glass substrate with digital correction, which contains a transconductance amplifier, counter, and digital correction circuit, has been designed for touch‐panel applications for 3‐μm low‐temperature polysilicon (LTPS) technology. The voltage difference as a result of a change in capacitance due to a touch event is converted to current by a transconductance amplifier. By charging and discharging the capacitor in the counter, the counter displays different digital‐output codes according to touch or non‐touch events. Furthermore, not only can the touch or non‐touch event be distinguished, but also the influence of LTPS process variation can be compensated by a digital correction circuit in the proposed readout circuit.     

FOS: a low-power cache organization for multicores

The Journal of Supercomputing - The cache hierarchy of current multicore processors typically consists of one or two levels of private caches per core and a large shared last-level cache. This...     

A low-power network for on-line diagnosis of heart patients

Implantable cardioverter defibrillators detect and treat dangerous cardiac arrhythmias. Current ICDs, however, cannot distinguish between some potentially fatal arrhythmias and benign conditions. Our system classifies intracardiac electrograms to detect such arrhythmias and uses analog techniques to meet the strict power and area requirements of implantable systems. A robust neural network architecture reduces the impact of noise, drift, and offsets inherent in analog approaches