900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA RF receiver ICs with a new mixer linearization method and optimization of integrated inductor for single balance mixer LO buffer

900 MHz CDMA, 1.8 GHz PCS, and 450 MHz CDMA RF receivers are implemented and measured. In order to reduce NRE cost and meet the demand of fast time-to-market, a metal-mask configurable method is applied for those receivers using only upper metals, contact and via layers. Also to reduce power consumption, a new mixer linearization method is proposed, along with an optimization methodology of an integrated inductor for a single balance mixer LO buffer, with respect to power consumption and silicon area. In order to apply the proposed inductor optimization methodology into metal-mask configurable circuits, inductor design considerations for metal-mask variant circuits are presented. With the proposed linearization technique and inductor optimization method, low power 900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA mixers are obtained. The proposed receivers are fabricated in a 0.35 μm SiGe BiCMOS process. In the 900 MHz CDMA case, measurement results of the proposed mixer show 12 dBm IIP3 and 10.2 dB conversion gain, and 7.5 dB SSB NF with 10.5 mA current consumption at 2.7 V supply voltage.     

Analysis and implementation of a CMOS even harmonic mixer with current reuse for heterodyne/direct conversion receivers

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP/sub 3/) of -5.01 dBm, and IIP/sub 3//dc of -6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.     

An integrated low power highly linear 2.4-GHz CMOS receiver front-end based on current amplification and mixing

A low power 2.4-GHz complementary metal oxide semiconductor (CMOS) receiver front-end using highly linear mixer based on current amplification and mixing is reported. In the proposed mixer, linearity is greatly improved by using current mirror amplifier and transconductance linearization using multiple gated transistors. Single IF direct conversion receiver (DCR) architecture is used to achieve higher level of integration and to relax the problem of DCR. The fully integrated receiver front end is fabricated in 0.18-/spl mu/m CMOS technology and HP3 of -9 dBm with a gain of 32 dB and noise figure of 6.5 dB are obtained at 8.8 mW power consumption.     

High-performance current bleeding CMOS mixer

A high-performance mixer, known as the amplifier-driven double-balanced Gilbert-cell mixer, is proposed and implemented in 0.18 mum RFCMOS technology. A class-A amplifier-based current bleeding source is used to amplify the local oscillator signal and improve transconductance of the transconductor stage. The conversion gain is measured to be 17.5 dB when the LO power is 14 dBm only. The measured noise figure is better than 12.5 dB. The chip area is 1.2 1.3 mm and the power consumption is 12 mA at 1.5 V supply voltage.     

Noise-Shaping Gain-Filtering Techniques for Integrated Receivers

In this paper, a new technique for realizing area-efficient, low-noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the passband of the filter. This is illustrated by implementing a programmable noise-shaped post-mixer gain-filtering circuit for a CMOS Mobile-TV tuner. The proposed circuits relax the noise-linearity tradeoff in the receiver chain by providing blocker rejection following the mixer outputs. The filter provides an in-band input referred noise density as low as 7.5 nV/sqrt(Hz). The measured out-of-band IIP3 values are 30 dBV and 31.5 dBV for the 3.8-MHz (DVB-H) and 750-kHz (ISDB-T) modes, respectively. Total current consumption is 5.5 mA from a 1.2-V supply. The gain of the block is programmable to be 0 dB, 8 dB, 14 dB, or 20 dB. The design occupies a die area of 0.28 mm² in a 65-nm CMOS process covering a frequency band of 700 kHz to 5.2 MHz as a universal mobile-TV integrated baseband gain-filtering solution.     

A wide band up-conversion mixer for cable television tuner

An up-conversion mixer implemented in a 0.35μm SiGe BiCMOS technology for a double conversion cable TV tuner is described, The mixer converts the 100MHz to 1000MHz band to the Intermediate Frequency of 1GHz above. The mixer meets the linearity and noise figure requirements for a TV tuner. The noise figure （IF） of 19.2-17.5dB, ldB compression of 12.1dBm, and gain of-1-0.7dB in the 900MHz band are achieved at a supply voltage of 5V. The power consumption is 47mW.     

1.9 GHz高线性度上混频器设计

介绍了采用0.35μm CMOS工艺实现的单边带上变频混频电路。该混频电路可用于低中频直接混频的PCS1900(1 850~1 910 MHz)发射器系统中。电路采用了multi-tanh线性化技术,可以得到较高的线性度。在单电源+3.3 V下,上混频器电流约为6 mA。从上混频电路输出级测得IIP3约8 dBm,IP1dB压缩点约为0 dBm。     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

A low power high linearity baseband for a direct conversation CMMB tuner

An analog baseband circuit made in a 0.35-μm SiGe BiCMOS process is presented for China Multimedia Mobile Broadcasting (CMMB) direct conversion receivers. A high linearity 8th-order Chebyshev low pass filter (LPF) with accurate calibration system is used. Measurement results show that the filter provides 0.5-dB passband ripple, 4% bandwidth accuracy, and -35-dB attenuation at 6 MHz with a cutoff frequency of 4 MHz. The current steering type variable gain amplifier (VGA) achieves more than 40-dB gain range with excellent temperature compensation. This tuner baseband achieves an OIP3 of 25.5 dBm, dissipates 16.4 mA under a 2.8-V supply and occupies 1.1 mm2 of die size.     

Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse

Receiver down-converter topologies are presented that provide simultaneous frequency conversion and baseband amplification within a mixer, in order to reduce power dissipation for a given dynamic range. The down-converted IF output of a mixer is reapplied to its input stage in a recursive manner, which significantly enhances the conversion gain, with current requirement determined primarily by the input transconductor of the mixer. Two down-converter topologies based on this technique are presented. One topology utilizes common-source NMOS devices as the RF input stage of the mixer, and reuses their transconductance for providing baseband gain. The second topology utilizes differential pairs as the RF input stage, and employs the transconductance of the tail current-source devices for baseband gain. The designs are implemented in a 0.13 mum CMOS technology and achieve peak conversion gains of 50 dB and 56 dB, with single side-band noise figures of 12.7 dB and 9.4 dB, and OIP3 values of 8 and 11 , respectively. They operate at a nominal supply of 1.2 V with bias current of 2.9 mA and 2.1 mA, respectively. The active die area is less than 0.1 mm for each design. Noise and linearity performance of the down-converters is analyzed, and the potential for enhancement of IIP3 through cancellation of nonlinear products is discussed.     

A monolithic double-balanced direct conversion mixer with an integrated wideband passive balun

This paper presents the design and performance characteristics of a 20-40 GHz monolithic double-balanced direct conversion mixer implemented using InGaP/GaAs HBT process. The compact MMIC mixer makes use of a Gilbert-cell multiplier and utilizes a broadband monolithic passive balun that has been developed for MMIC applications. The new balun makes use of multidielectric layer structure to achieve a broadband performance in a simple coplanar configuration. A measured return loss better than 15 dB, with a maximum insertion loss of 4.5 dB including the 3-dB power splitting loss has been achieved over the band from 15 to 45 GHz. Operated as a downconverter mixer, the newly developed direct conversion mixer achieves a measured conversion gain of 16 dB given an RF signal at 30 GHz, LO drive of 5 dBm and a downconverted baseband signal at 10 MHz. The mixer IP3 occurs at an output power of 4 dBm while the IP2 occurs at an output power of 11 dBm.     

A wideband CMOS VGLNA based on single-to-differential stage and resistive attenuator for TV tuners

A wideband CMOS variable gain low noise amplifier(VGLNA) based on a single-to-differential(S2D) stage and resistive attenuator is presented for TV tuner applications.Detailed analysis of input matching,noise figure(NF) and linearity for S2D is given.A highly linear passive resistive attenuator is proposed to provide 6 dB attenuation and input matching for each gain stage.The chip was fabricated by a 0.18μm 1P6M CMOS process, and the measurements show that the VGLNA covers a gain range over 36.4 dB and achieves a maximum gain of 21.3 dB,a minimum NF of 3.0 dB,an IIP3 of 0.9 dBm and an IIP2 of 26.3 dBm at high gain mode with a power consumption less than 10 mA from a 1.8 V supply.     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.     

A Single Transistor‐Level Direct‐Conversion Mixer for Low‐Voltage Low‐Power Multi‐band Radios

A CMOS direct‐conversion mixer with a single transistor‐level topology is proposed in this paper. Since the single transistor‐level topology needs smaller supply voltage than the conventional Gilbert‐cell topology, the proposed mixer structure is suitable for a low power and highly integrated RF system‐on‐a‐chip (SoC). The proposed direct‐conversion mixer is designed for the multi‐band ultra‐wideband (UWB) system covering from 3 to 7 GHz. The conversion gain and input P1dB of the mixer are about 3 dB and ?10 dBm, respectively, with multi‐band RF signals. The mixer consumes 4.3 mA under a 1.8 V supply voltage.     

A dual-b and RF front-end of direct conversion receiver for wireless CDMA cellular phones with GPS capability

A highly integrated direct conversion receiver for cellular code division multiple access (CDMA) and GPS applications is successfully developed using a 0.5-/spl mu/m SiGe BiCMOS technology. The receiver consists of two low-noise amplifiers (LNAs), a dual-band mixer, two voltage-controlled oscillators (VCOs), a local-oscillator signal generation block, and channel filters. The CDMA LNA achieves a noise figure of 1.3 dB, an input-referred third-order intercept point (IIP3) of 10.9 dBm, and a gain of 15.3 dB with a current consumption of 9.8 mA in the high-gain mode. The mixer for the CDMA mode achieves an uncalibrated input-referred second-order intercept point of 53.7 dBm, an IIP3 of 6.4 dBm, a noise figure of 7.2 dB and a voltage gain of 37.2 dB. The phase noise of the CDMA VCO is approximately -133 dBc/Hz at a 900-kHz offset from a 1.762-GHz operating frequency. It exceeds all the CDMA requirements when tested on a handset.     

A Low LO Power Mixer Utilizing the Body Effect

We propose a single-stacked CMOS mixer that can operate at low local oscillator (LO) power condition with a new switching mechanism. Gating the body terminal makes it possible for the mixer to operate in a more ideal switching mode by utilizing the body effect. Biasing at near pinch-off region gives rise to beneficial aspect, low power dissipation. This circuit is composed of all PMOS transistors which draw only 0.275 mA from a supply voltage of 1.8 V. This circuit features gain and noise enhancement characteristic, low power consumption, and simple topology. The proposed mixer achieves conversion gain of 18 dB, noise figure of 9.1 dB with 0 dBm LO power, and power consumption as low as 0.5 mW.     

宽带低噪声混频器的设计

文章利用安捷伦公司的ADS仿真软件,设计了一款应用于GNSS接收机射频前端的Gilbert混频器芯片,它的工作电压都为3.3V,中频输出口外接负载为800Ω,具有面积小、噪声系数低的特点。通过优化设计,在频率从1~1.6GHz的范围内,获得了超过15dB的转换增益,以及4dB的噪声系数,输入1dB增益压缩点(P-1dB)为-17dBm,功耗为29mW。     

A SiGe BiCMOS transmitter module for IMT2000 applications

This paper describes a Tx module for IMT2000 applications consisting of an up-conversion mixer and a variable-gain driver amplifier. The up-conversion mixer, based on the Gilbert active topology has a power gain of 4.8 dB and consumes 15-mA current from a 3-V supply. The variable-gain driver amplifier comprises a gain-controlled stage of the current steering structure and a common emitter stage, and has a variable-gain range of over 30 dB with 30.3-mA current consumption. The Tx module achieves a gain error of less than 1.2 dB over a 30-dB gain range, an output IP3 of 25 dBm, and an output PI dB of 7.4 dBm at the maximum gain of 24.5 dB. It occupies 1.0 /spl times/ 1.2 mm.     

0.5-25 GHz inductorless single-ended resistive mixer in 0.13 μm CMOS

A wideband inductorless resistive down-conversion mixer in 0.13 μm CMOS technology is presented. The mixer provides a conversion loss of 9?11.7 dB over a frequency range of 0.5?25 GHz at LO power of 6 dBm. The circuit exhibits an input-referred 1 dB compression point and IIP3 of 4.7 and 11.5 dBm, respectively. The mixer consumes only 0.2 mA from 1.5 V for biasing. The isolation between the ports is higher than 10 dB for the whole frequency range. The circuit is realised without inductors, thus offering very wide bandwidth. The chip size including the pads is 0.23 mm², and the circuit active area is only 0.014 mm².     

The Design of Low LO-Power 60-GHz CMOS Quadrature-Balanced Self-Switching Current-Mode Mixer

This letter describes the analysis and measurement of a complementary metal-oxide semiconductor (CMOS) quadrature-balanced current-mode mixer with a 90^deg branch-line hybrid coupler and self-switching current-mode devices. The proposed mixer, using 0.13 mum 1P8M CMOS technology, can downconvert a 60 GHz RF signal to a 2 GHz intermediate frequency (IF) signal, with a local-oscillator power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1 dB and an input-referred 1 dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve -37 dB while using 3 mA from a supply voltage of 1.2 V.