基于扫描森林结构的种子编码方案

扫描森林是一种有效的扫描结构，它能够大幅度地降低测试应用开销、测试功耗以及测试数据容量。该文针对采用扫描森林结构的待测电路提出了一种新的种子编码方案。在该方案中，伪随机测试向量覆盖电路中的易测故障，使用ATPG对剩余故障生成确定性测试向量，将其中某一测试向量对应的种子编码为LFSR扩展成该向量需要运行的时钟周期数。实验结果表明，提出的方案能大幅度地降低种子存储数据量，最大降幅达到了83.3％。     

BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

This paper presents a built-in self-test(BIST) scheme for detecting all robustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit.The test pattern generator(TPG) generates all n.2^n single-input-change(SIC) orderd test pairs design is universal,i.e.,independent of the structure and functionality of the CUT.A counter that counts the number of alternate transitions at the output of the CUT,is used as a signature analyzer(SA).The design of TPG and SA is simple and no special design-or synthesis-for-testability techniques and /or additional control lines are needed.     

基于伪随机测试的模数混合信号内建自测试法

利用伪随机序列作为测试激励,通过计算输入输出的互相关函数得到K维特征空间,在特征空间的基础上进行分析,判别电路有无故障,实验证明该方法简单可行,且提高了测试的效率和正确性,适用于模拟及混合信号测试,适用于混合信号电路的内建自测试（BIST）。     

A Universal BIST Approach for Virtex-Ultrascale Architecture

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs’ capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.     

ClassBench: a Framework for Automated Class Testing

In contrast to the explosion of activity in object-oriented design and programming, little attention has been given to object testing. We present a novel approach to automated testing designed especially for collection classes. In the ClassBench methodology, a testgraph partially models the states and transitions of the Class-Under-Test (CUT) state/transition graph. To determine the expected behavior for the test cases generated from the testgraph, the tester develops an oracle class, providing essentially the same operations as the CUT but supporting only the testgraph states and transitions. Surprisingly thorough testing is achievable with simple testgraphs and oracles. The ClassBench framework supports the tester by providing a testgraph editor, automated testgraph traversal, and a variety of utility classes. Test suites can be easily configured for regression testing–where many test cases are run–and debugging–where a few test cases are selected to isolate the bug. We present the ClassBench methodology and framework in detail, illustrated on both simple examples and on test suites from commercial collection class libraries. © 1997 John Wiley & Sons, Ltd.     

Exploiting deterministic TPG for path delay testing

Detection of path delay faults requires two-pattern tests.BIST technique provides a low-cost test solution.This paper proposes an approach to designing a cost-effective deterministic test pattern generator(IPG) for path delay testing.Given a set of pre-generated test-pattern generator(TPG) for path delay testing.Given a set of pre-generated test-pairs with pre-determined fault coverage,a deterministic TPG is synthesized to apply the given test-pair set in a limited test time.To achieve this objective,configuable linear feedback shift register(LFSR)structures are used.Techniques are developed to synthesize such a TPG.which is used to generate an unordered deterministic test-pair set.The resulting TPG is very efficient in terms of hardware size and speed performance.SImulation of academic benchmark circuits has given good results when compared to alternative solutions.     

一种基于ALM的Modem自动化测试系统

自动化测试能够减少手动测试带来的不便和干扰,提高测试效率。测试自动化是软件测试的一大趋势。本文介绍了一种基于ALM工具的Modem自动化测试系统,重点介绍其系统框架、处理流程及软件架构,最后通过一个具体的测试例进行了进一步说明及验证。     

A star network approach in heterogeneous multiprocessors system on chip

Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex links (FSL) as basic structure to connect the scheduler with heterogeneous processing elements, including processors and hardware IP cores. Blocking and nonblocking application interfaces are provided for high level programming. We built a prototype system on FPGA to evaluate the transfer time and hardware cost of the proposed star network architecture. Experiment results demonstrated that the average transfer time for each word could be reduced to 7 cycles, which achieves 14× speedup against state-of-the-art shared memory literatures. Moreover, the star network cost only 1.2?% Flip Flops and 2.45?% LUTs of a single FPGA.     

ManTS:实时可扩展MANET动态测试系统

移动adhoc网络(MANET)的协议调试十分重要,而其多跳性和节点的移动性使协议的调试十分困难。传统的仿真工具在仿真大规模移动多跳网时往往实时性和可扩展性不能满足被测协议运行时对网络环境的要求。ManTS(MANETTestSystem)是一个动态的MANET测试系统,采取分布式的体系结构,利用虚拟传输的方法。被测协议不需要修改,就能直接在ManTS实时运行;ManTS中的节点数可以动态变化,以满足大规模测试的需要。     

边界扫描技术在FPGA测试中的应用

边界扫描技术是标准化的可测试性设计技术,它提供了对器件的功能、互连及相互间影响进行测,极大地方便了对于复杂电路的测试。文章针对XCV600_HQ240,介绍了边界扫描的基本结构、边界扫描测试操作流程、测试接口和IEEE 1149.1标准规定的数据寄存器和指令寄存器,结合FPGA芯片的BSDL文件进行边界扫描配置和测试。     

一种基于SAT的FPGA映射优化算法

为了提高FPGA技术映射算法的质量,提出了一种基于布尔可满足性(SAT)的算法,在实现系统功能的前提下,可以将一个子电路映射到数量最少的查看表中。通过将该算法迭代应用于已经完成映射的电路局部,在许多情况下,可以使用更少的查看表来完成。     

Employing static information in the generation of test cases

A commonly used approach for detecting defects in a program is to generate a suite of test inputs which exercises the entire program under a given testing criterion. Current techniques to generate test cases automatically that satisfy a testing criterion choose test input data by considering the testing requirements in an arbitrary order. In this paper, a technique is presented that groups the requirements and orders the generation of the test cases to reduce the number of test cases generated. The grouping is based on the statically determined property of post-dominance. Test cases for each group are generated taking into account requirements for other groups. The use of this technique to generate test cases can be expected to produce fewer test cases that have to be retained with the software. A smaller number of test cases will require less effort and resources to test the software. The technique is especially useful in the maintenance environment, whether retesting of a changed program is done exhaustively or incrementally. The technique not only attempts to minimize the number of test cases generated but also reduces the effort to generate the test cases using the concept of a program slice.     

FPGA测试技术及ATE实现

随着FPGA的规模和复杂性的增加,测试显得尤为重要。介绍了SRAM型FPGA的结构概况及FPGA的测试方法,以Xilinx公司的spartan3系列芯片为例,利用检测可编程逻辑资源的多逻辑单元（CLB）混合故障的测试方法,阐述了如何在自动测试系统（ATE）上实现FPGA的在线配置以及功能和参数测试,为FPGA面向应用的测试提供了一种可行的方法。     

就地化保护智能管理单元自动测试系统设计

为进一步提升智能管理单元研发测试的质量和效率,提出了就地化保护智能管理单元自动测试系统的构建方案。给出了智能管理单元自动测试系统的总体设计思路。设计了自动测试系统的硬件框架;采用模块化、层次化的软件体系架构,增强了测试系统的扩展性和可维护性;详细介绍了自动测试系统的功能实现流程和测试操作流程。根据测试项目全自动生成测试用例,构建智能管理单元运行仿真环境、完成故障模拟,采用多线程等计算机技术,高效、可靠地实现了对智能管理单元的全自动闭环测试。该自动测试系统的主要创新点在于全自动生成用例、规范测试流程及模拟电力系统故障。实际应用表明,该设计能够显著提高测试质量和测试效率,其层次化的软件架构设计及规范化的流程设计对其他自动化控制系统的研制也有一定的参考意义。     

基于DSP的数字检波设计及实现

该文介绍了一种在实时频谱分析仪环境中,基于DSP的数字检波设计方案,给出了如何利用DSP实现多种视频检波等关键技术的实现原理与方法。传统方案通常选择利用FPGA的童配置来实现检波与其它功能模式的切换,而重配置较为复杂,导致模式切换速度慢,不稳定因素增加。该设计明显减少了测试模式切换所带来的重配置操作,从而降低了系统的复...     

用全速电流测试检测AT89C51微处理器的实验研究

全速电流测试是一种新的电路测试方法,现以AT89C51微处理器为例,说明用全速电流测试进行微处理器测试的可能性.在实验中,让微处理器重复执行选定的指令序列,以普通的万用数字电流表测量微处理器消耗的平均电流,并给出了指令序列的产生方法.实验结果表明,用全速电流测试在指令级对AT89C51微处理器进行测试是可行的.通过测试所有的数据通路,不但可以检测数据通路的故障,而且可以检测由于控制错误而引起的数据传送错误.     

一种FPGA验证与测试的方法介绍

如何快速开发FPGA测试平台以实现FPGA验证与测试是本文的研究重点。基于PC、ATE与自制应用型DUT板,对FPGA验证与测试开发技术进行研究。PC主要完成测试程序下载与调试验证工作,自制应用型DUT板实现对FPGA的配置,ATE等待FPGA配置完成后进行信号输入与输出验证。基于该理论对Xilinx公司的XC2S200进行了实验,实验表明该方法可行并能快速实现测试开发与芯片验证,且具有很好的通用性,可用于其他FPGA芯片的测试、研究与验证。     

A framework for intelligent test data generation

Test data generation using traditional software testing methods generally requires considerable manual effort and generates only a limited number of test cases before the amount of time expanded becomes unacceptably large. A rule-based framework that will automatically generate test data to achieve maximal branch coverage is presented. The design and discovery of rules used to generate meaningful test cases are also described. The rule-based approach allows this framework to be extended to include additional testing requirements and test case generation knowledge.This work was supported in part by George C. Marshall Space Flight Center, NASA/MSFC, AL 35812 (NASA-NCC8-14).     

基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术,提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器,同时给所有扫描链输入测试向量,并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集,并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路,利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测,从而实现被测电路和故障完全检测。