国外InP HEMT和InP HBT的发展现状及应用

在毫米波段,InP基器件由于其具有高频、高功率、低噪声及抗辐射等特点,成为人们的首选,尤其适用于空间应用.InP HEMT和InP HBT已在卫星、雷达等军事应用中表现出了优异的性能.分别介绍了InP HEMT和InP HBT器件及电路的发展现状,现在能达到的最高性能及主要生产公司等,其中InP HEMT又分别按低噪声和功率进行了详细介绍.介绍了它们在军事上的主要应用,以具体的应用实例介绍了在卫星相控阵雷达系统天线中的T/R模块中、航天器和地面站的接收机中、以及雷达和通信系统中的应用情况、达到的性能及可靠性等.并根据国外InP器件和电路的发展现状总结了其未来发展趋势.     

LPE growth of InP/InGaAs/InP DH wafers on (100) InP substrates

An InP/InGaAs/InP double heterostructure wafer is grown directly on a (100) InP substrate using very low temperature LPE growth. This crystal exhibits a thin transition layer at a InP-InGaAs interface because of dissolution of the ternary layer.     

InGaAs（InAIAs）／InP和InP／InAIAs湿法选择腐蚀研究

介绍了两种选择腐蚀液对InGaAs（InAlAs）／InP和InP／InAlAs异质结构材料选择腐蚀的实验结果，重点介绍在InAlAs上面生长InP的湿法选择腐蚀，用HCl：H3PO4：CH3COOH系列腐蚀液，InP／InAlAs选择比大于300。InP／InAlAs湿法选择腐蚀的结果可以很好应用到OEIC芯片制作中，并取得了较好的器件及电路结果。     

InP Schottky-gate field-effect transistors

MESFET's with gates 1 µm long were fabricated in LPE layers of InP on Cr-doped InP substrates. The quality of the LPE material is characterized by an electron concentration of 4 × 10¹⁵cm^-3with a mobility of 2.6 × 10⁴cm²V^-1s^-1at 77 K for growths from undoped melts. The devices have current gain cutoff frequencies of 20 GHZ or somewhat larger. This value is greater than that of the best analogous GaAs MESFET bya factor of 1.5. A factor of 1.3 is predicted on the basis of a simple theory. The highest power gain cutoff frequency, fmax, for the InP device is 33 GHz which is somewhat smaller than that of the best analogous GaAs device. The lowest minimum noise figure at 10 GHz for these first InP devices is 3.9 dB with an associated gain of 4.8 dB. The best result for the GaAs counterpart is 3.2 dB with an associated gain of 7.8 dB. The power gain of the InP device suffers compared to the GaAs device because of degenerative feedback resulting from a large gate-to-drain capacitance and because of a small output resistance. If the magnitudes of these two equivalent circuit elements were the same for MESFET's in the two materials, fmaxfor the InP device would be more than double its present value.     

InGaAs(InAlAs)/InP和InP/InAlAs湿法选择腐蚀研究

介绍了两种选择腐蚀液对InGaAs(InAlAs)I/nP和InPI/nAlAs异质结构材料选择腐蚀的实验结果,重点介绍在InAlAs上面生长InP的湿法选择腐蚀,用HClH∶3PO4C∶H3COOH系列腐蚀液,InPI/nAlAs选择比大于300。InPI/nAlAs湿法选择腐蚀的结果可以很好应用到OEIC芯片制作中,并取得了较好的器件及电路结果。     

Pseudomorphic AlInP/InP heterojunction bipolar transistors

Novel InP-based heterojunction bipolar transistors (HBTs) using an AlInP pseudomorphic emitter, together with an InP base and collector, have been fabricated. By using InP as both base and collector, the advantage of high electron velocity and high breakdown field of InP collectors are obtained without the problem associated with the energy barrier between the more standard InGaAs/InP base and collector heterojunction. Epitaxial layers were grown by gas-source molecular beam epitaxy (GSMBE). The 200 Å pseudomorphic emitter had an aluminium fraction of 15%, sufficiently suppressing hole injection from the base. The DC gain for 40×40 μm² devices reached 18. The breakdown voltage BV_CEO of 10 V is an improvement over devices with InGaAs base and collector layers     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n -InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n -InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n -InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

Growth and Luminescence of Polytypic InP on Epitaxial Graphene

Van der Waals epitaxy is an attractive alternative to direct heteroepitaxy where the forced coherency at the interface cannot sustain large differences in lattice parameters and thermal expansion coefficients between the substrate and the epilayer. Herein, the growth of monocrystalline InP on Ge and SiO₂/Si substrates using graphene as an interfacial layer is demonstrated. Micrometer‐sized InP crystals are found to grow with interfaces of high crystalline quality and with different degrees of coalescence depending on the growth conditions. Some InP crystals exhibit a polytypic structure, consisting of alternating zinc‐blende and wurtzite phases, forming a type‐II homojunction with well (barrier) width of about 10 nm. The optical properties, investigated using room temperature nano‐cathodoluminescence, indicate the signatures of the direct optical transitions at 1.34 eV across the gap of the zinc‐blende phase and the indirect transitions at ≈ 1.31 eV originating from the alternating zinc‐blende and wurtzite phases. Additionally, the InP nanorods, found growing mainly on the graphene/SiO₂/Si substrate, show optical transition across the gap of the wurtzite phase at ≈ 1.42 eV. This demonstration of InP growth on graphene and the correlative study between the structure and optical properties pave the way to develop hybrid structures for potential applications in integrated photonic and optoelectronic devices.     

Reliability of InGaAs/InP based separate absorption grading multiplication avalanche photodiodes

An overview over typical defects and reliability aspects regarding the operation of InGaAs/InP avalanche photodiodes for the use in fiber-optic communication systems is given.Measurements regarding the performance and stability of different types of top illuminated InGaAs/InP Separate Absorption Grading Multiplication avalanche photodiodes have been compared with special emphasis on the homogeneity of the photoresponse. High resolution scanning optical microscopy measurements at different wavelengths allowed to identify specific technological problems. Guard ring misalignment resulting in increased responsivity of the junction perimeter have been found on devices from one manufacturer.The responsivity images of the active area of some of the investigated photodiodes showed sharp peaks due to microplasma formation. The impact of these microplasmas on dark current and photocurrent of the devices has been investigated in detail.A step-stress test performed at successively increasing temperatures resulted in the catastrophic failure of the tested devices from one family. An analysis of the dark current-voltage characteristics before and after degradation leads to the conclusion that a modification of the semiconductor-insulator interface properties caused a dramatic increase in the surface leakage currents.     

GaAs/InP键合电学性质的研究

III-V族晶片键合技术对于光电器件的制备和实现光电集成有着重要意义,然而,对于键合界面的电学性质仍然研究较少。采用热电子发射理论,基于界面态能级在禁带中连续分布的假设,根据分布函数结合I-V测试曲线可建立键合结构的界面态计算模型。利用该模型对不同条件下键合的InP/GaAs电学性质做了分析比较,通过初始势垒的确定,计算并比较了各种键合条件下GaAs/InP键合时的界面电荷及界面态密度。实验及计算结果表明疏水处理表面550度条件下键合晶片对有更低的表面初始势垒和更少的界面态密度,因而具有更好的I-V特性。     

Charge storage in InAlAs/InGaAs/InP floating gate heterostructures

Charge retention in floating gate InAlAs/InGaAs/InP field effect transistors is limited by lateral electron motion along the storage channel, a different direction for motion than found for AlAs/GaAs devices. Storage times as a function of temperature for the InP based alloy devices are reported and compared with similar AlAs/GaAs devices by using Poisson equation models.<>     

InP/Si键合技术研究进展

InP材料及其器件的研制是近年来研究热点之一,而键合技术又是光电子集成研究领域内一项新的制作工艺。利用键合技术结合离子注入技术可以InP薄膜及器件集成到Si衬底上,改善机械强度,降低成本,具有非常诱人的应用前景。概括地介绍了近年来InP在Si上的键合工艺及层转移技术研究进展,并对InP和Si的几种键合工艺进行了分析。降低InP和Si键合温度,进行低温键合是其发展趋势。比较几种键合技术,利用等离子活化辅助键合是降低键合温度的有效途径。     

磷化铟的化学机械抛光技术研究进展

磷化铟单晶作为一种重要的外延层衬底材料被广泛应用于光电器件.衬底外延生长和电子器件制备要求磷化铟晶片表面具有极低的表面粗糙度、无表面/亚表面损伤和残余应力等,需对磷化铟晶片表面进行抛光加工,其表面质量决定了后续的外延层质量并最终影响磷化铟基器件的性能.综述了磷化铟晶体化学机械抛光(CMP)技术进展;介绍了磷化铟表面的化学反应原理、CMP去除机理;详细分析了磷化铟抛光液组分及pH值、抛光工艺参数(抛光压力、抛光盘转速、抛光垫特性、磨料种类、粒径及浓度)等对磷化铟抛光质量的影响;介绍了磷化铟抛光片的清洗工艺,并对磷化铟CMP的后续研究方向提出一些建议.     

High-Current-Gain InP/GaInP/GaAsSb/InP DHBTs With fT = 436 GHz

Combining a pseudomorphically strained (Ga,In)P emitter with a GaAs_0.6Sb_0.4 base effectively eliminates the emitter heterojunction type-II conduction band offset in InP/GaAsSb double heterojunction bipolar transistors (DHBTs). A peak f_T of 436 GHz at J_C = 10 mA/mum², with BV_CEO = 3.8 V, is achieved with 0.6 times 5 mum² InP/GalnP/GaAsSb DHBTs with a 75-nm InP collector. Compared to a binary InP emitter, the (Ga,In)P emitter doubles the DC current gain from 166 to 338 for otherwise identical devices. These are the highest DC current gain and cutoff frequencies to date in uniform base GaAsSb DHBTs. The gain improvement reported here will greatly facilitate device design tradeoffs that are encountered while scaling InP/GaAsSb DHBTs toward higher frequencies by allowing higher base doping levels and smaller emitter geometries.     

VPE growth of high purity and high uniformity InGaAs/InP epilayers on InP

PIN and avalanche photodiodes are vital component parts of today's optical communication systems. For these, InP/InGaAs/InP heteroepitaxial structures are required. To improved the quality and yield of these devices, the epitaxial wafers must be of very high purity and uniformity. At Sumitomo Electric we have grown the above mentioned epitaxial layers by the chloride VPE method, which is safe and has a usefully high growth rate. This article describes the growth technique and the characterization of high uniformity and high purity InGaAs/InP epilayers.     

Chemically etched-mirror GaInAsP/InP lasers--Review

Detailed results on stripe GaxIn1-xAsyP1-y/InP lasers (lambda = 1.3 mum) with chemically etched-mirrors are reviewed. These devices are fabricated from GaInAsP/InP wafers grown by liquid phase epitaxy. A simple stripe laser structure with one etched mirror and one cleaved mirror is proposed. Monolithic passivation has been achieved using a Si3N4film and metal coatings on the etched facets. These processes not only increase the reflectivity of the etched mirrors, resulting in threshold currents even lower than uncoated cleaved devices, but also ease the problem of bonding of the chips on heat sinks. CW operation at room temperature has been achieved. Threshold currents of devices with 10 μm stripe electrodes were about 180-200 mA. Short cavity lasers and integrated monitoring detectors have also been demonstrated.     

300 GHz InP/GaAsSb/InP double HBTs with high current capability andBVCEO>6 V

We report MOCVD-grown NpN InP/GaAsSb/InP abrupt double heterojunction bipolar transistors (DHBTs) with simultaneous values of f _T and f_MAX as high as 300 GHz for J_C=410 kA/cm² at V_CE=1.8 V. The devices maintain outstanding dynamic performances over a wide range of biases including the saturation mode. In this material system the p+ GaAsSb base conduction band edge lies 0.10-0.15 eV above the InP collector conduction band, thus favoring the use of nongraded base-collector designs without the current blocking effect found in conventional InP/GaInAs-based DHBTs. The 2000 Å InP collector provides good breakdown voltages of BV_CEO=6 V and a small collector signal delay of ~0.23 ps. Thinner 1500 Å collectors allow operation at still higher currents with f_T>200 GHz at J_C=650 kA/cm²     

MOCVD生长的平面型InGaAs／InP PIN光电探测器件

讨论了采用MOCVD技术生长的平面型InGaAs/InPPIN器件的光学特性及制备工艺。通过引入InP窗口层并制备合适的抗反射膜,大大提高了器件的量子效率,达到～96%,采用平面型结构有可能改善器件的稳定性和可靠性。     

Undoped InP/InGaAs heterostructure insulated-gate FET's grown byOMVPE with PECVD-deposited SiO2 as gate insulator

The fabrication and performance of InP/InGaAs insulated-gate FETs which use a heterojunction to isolate the channel electrons from the semiconductor-insulator interface are discussed. Plasma-enhanced chemical vapor deposition (PECVD) was used to deposit SiO₂ on InP to form the gate insulator. Since the device structure is undoped, channel electrons are accumulated by the gate-induced field across the insulator. Extrinsic transconductances of 130 mS/mm (300 K) and 210 mS/mm (77 K) were achieved for 1.5- μm gate-length devices. Gate-drain breakdown voltages in excess of 20 V were also measured     

2-D particle modelling of the InP MISFET

Taking into account two-dimensional effects and non-stationary transport dynamics, InP-MISFETs with submicron gates have been modelled. Contrary to similar Silicon MOSFETs, channel pinch-off rather than velocity limitation is the drain current saturation mechanism. In addition the drain current and the cut-off frequency are approximately 5 times higher in InP. In order to compare the calculated channel mobility to experimental values, also a 2-μm InP MISFET with realistic doping profiles has been modelled. It appears that interface potential well fluctuations arising from surface roughness or random distributed oxide charges are the main mechanism responsible for channel mobility reduction. Owing to the energy dependance of these mechanisms, the potentially high mobility value of III–V MIS devices can be drastically suppressed.